Thin Film Transistor Stacked Gate Insulator
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Solution Overview
Problem
Conventional thin film transistors face limitations due to high current leakage and impractical fabrication times of silicon oxide gate insulating layers, which hinder the production of high-performance devices with other semiconductor materials.
Innovation Solution
A thin film transistor design featuring a stacked gate insulating layer comprising an aluminum oxide layer and a metal oxide layer, fabricated using a solution process with specific precursor solutions and annealing, which improves performance and simplifies the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon oxide is used as the gate insulating layer, then the device can be manufactured with conventional processes, but the current leakage is high and device performance is limited
Solution Approach 1:
The patent employs a composite gate insulating layer structure consisting of multiple metal oxide layers (such as hafnium oxide, aluminum oxide, silicon oxide) with different properties. This composite structure achieves low current leakage and high dielectric constant while maintaining compatibility with conventional manufacturing processes, resolving the contradiction between reliability and ease of manufacture.
Solution Approach 2:
The patent changes the material parameters of the gate insulating layer by using metal oxides with high dielectric constants (k-value) instead of conventional silicon oxide. This parameter change reduces current leakage and improves device performance while the solution process maintains manufacturing feasibility.
2Reliability
If atomic layer deposition (ALD) process is used to densely form the gate insulating layer, then device performance is improved, but the fabrication time becomes too long for practical application
Solution Approach 1:
The patent replaces the complex ALD deposition process with a simpler solution-based spin coating method. The metal oxide layers are formed by applying precursor solutions and annealing, which significantly reduces fabrication time while achieving dense, high-performance gate insulating layers suitable for practical manufacturing.
Solution Approach 2:
The patent changes the formation process parameters from ALD (layer-by-layer atomic deposition) to solution processing (bulk deposition followed by annealing). This parameter change maintains the dense structure and high performance of the gate insulating layer while reducing the number of process steps and total fabrication time.
3Adaptability or versatility
If conventional gate insulating layers are used, then the manufacturing process is simple, but the device cannot achieve high performance with non-silicon semiconductor materials
Solution Approach 1:
The patent creates a universal gate insulating layer structure using metal oxides that can interface with various semiconductor materials including oxide semiconductors, silicon, and other materials. The solution processing method and metal oxide composition provide broad material compatibility while maintaining high device performance, achieving universality across different semiconductor platforms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-performance thin film transistors with reduced current leakage and faster fabrication, suitable for use in display devices like LCDs and OLEDs, with improved charge mobility and stability.
Implementation Method 1
a stacked gate insulating layer that is positioned between the gate electrode and semiconductor. The stacked gate insulating layer includes an aluminum oxide layer
Implementation Method 2
The forming the stacked gate insulating layer may be performed by a solution process
Implementation Method 3
The forming the stacked gate insulating layer may include annealing at about 100° C. to about 400° C.
Data Source
AI summary
Disclosed is a thin film transistor that includes a gate electrode, a semiconductor overlapping with the gate electrode, a source electrode that is electrically connected to the semiconductor, a drain electrode that is electrically connected to the semiconductor and faces the source electrode, and a stacked gate insulating layer that is positioned between the gate electrode and semiconductor. The stacked gate insulating layer includes an aluminum oxide layer. A method of manufacturing the same and a display device including the thin film transistor are also disclosed.