Thin Film Transistor With Stacked Source And Drain Layers
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Solution Overview
Problem
The existing thin film transistors (TFTs) have a restricted channel length due to manufacturing limitations, which hinders the increase in current output and development of electronic devices.
Innovation Solution
The TFT design allows for adjustable source-to-drain distance by forming source and drain from different conductive layers, enabling flexible channel length adjustment and reducing the channel length to less than 3 μm, thereby improving carrier mobility and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source and drain are formed by patterning the same conductive layer, then the manufacturing process is simple, but the horizontal distance from source to drain cannot be further shortened below 3 μm
Solution Approach 1:
The source and drain are formed from different conductive layers instead of the same layer, segmenting the formation process into separate steps. This allows the source to be formed in one layer and the drain in another layer, enabling the horizontal distance between them to be reduced below the conventional 3 μm limit while maintaining manufacturing feasibility through sequential patterning and etching processes.
Solution Approach 2:
The invention transitions from a two-dimensional patterning approach (source and drain in the same plane) to a three-dimensional stacked approach (source and drain in different layers). By utilizing the vertical dimension to separate source and drain formation, the horizontal distance between them can be minimized while still allowing adequate separation through layer stacking, thus resolving the contradiction between manufacturing simplicity and channel length reduction.
2Power
If the channel length is reduced to increase current output, then the current output increases, but the source and drain separation becomes insufficient
Solution Approach 1:
By forming source and drain in different conductive layers stacked vertically, the invention utilizes the third dimension (vertical space) to provide adequate separation between source and drain. This allows the horizontal distance to be reduced for higher current output while the vertical layering maintains sufficient electrical isolation and physical separation, preventing short-circuiting and ensuring proper device operation.
Solution Approach 2:
The invention changes the spatial arrangement parameter from coplanar (same layer) to stacked (different layers), which fundamentally alters how separation is achieved. This parameter change enables simultaneous optimization of both current output (through reduced horizontal distance) and source-drain separation (through vertical layering), resolving the contradiction between these two requirements.
3Area of stationary object
If the horizontal distance from source to drain is shortened, then the channel area is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
By segmenting the source and drain formation into separate process steps using different conductive layers, the invention reduces the alignment precision requirements compared to forming both in the same layer. Each layer can be patterned and aligned independently with its own reference structures, allowing for more relaxed overall alignment tolerances while achieving smaller TFT footprints through the stacked configuration.
Data Source
AI summary
A thin film transistor (TFT) and a pixel structure having the TFT are provided. The TFT is configured on a substrate. Besides, the TFT includes a gate, a gate insulation layer, a source, a channel layer, and a drain. The gate insulation layer covers the gate and the substrate. The source is configured on a portion of the gate insulation layer. The channel layer is configured on the gate insulation layer and covers a portion of the source located above the gate. The drain is configured on and electrically connected to the channel layer.