TFT Array Substrate Stepped Contact Holes Uniform Cell Thickness
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Solution Overview
Problem
Conventional TFT array substrates for liquid crystal display panels suffer from display quality deterioration due to uneven cell thickness caused by the configuration of contact holes, which leads to issues with uniform light irradiation and sealing, and hinders the reduction of inter-wiring distances in the periphery area.
Innovation Solution
The TFT array substrate is designed with gate bus lines and source bus lines formed from different metal materials, where connection conductors cover branch-wiring via holes that overlap with main wirings, eliminating off-wiring portions and ensuring a uniform wiring layer thickness, thereby preventing uneven cell thickness and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are configured in conventional TFT array substrates, then wiring connections are established, but uneven cell thickness occurs causing display quality deterioration
Solution Approach 1:
The patent transitions from a planar contact hole configuration to a stepped configuration that utilizes vertical dimensionality. The first contact hole portion extends to the first wiring layer while the second contact hole portion extends further to the second wiring layer, creating a stepped structure that maintains uniform cell thickness by compensating for the varying depths required to reach different wiring layers.
2Productivity
If inter-wiring distances are reduced in the periphery area, then driver circuit output characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different contact hole configurations to different regions: in the periphery area where driver circuits are located, stepped contact holes are used to accommodate reduced inter-wiring distances while maintaining electrical connections. This localized application allows improved driver circuit performance without requiring the entire substrate to use the complex stepped configuration.
Data Source
AI summary
An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.