Thin-Film Transistor Stress Layers for Higher Carrier Mobility

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Solution Overview

Problem

Thin film transistors (TFTs) made of oxide semiconductors face challenges in enhancing on-current due to limitations in mechanical stress induction methods, which are crucial for improving charge carrier mobility and device performance.

Innovation Solution

The introduction of metallic liners that induce compressive or tensile stress in the end portions of semiconducting material layers, either through deposition of stress-generating metallic materials or by implanting dopants to alter the lattice constant, thereby generating mechanical stress within the channel portion of the TFTs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If mechanical stress induction methods are used to enhance on-current in TFTs, then charge carrier mobility is improved, but the existing methods have limitations in effectiveness and applicability

Engineering Contradiction:

Improveon-currentVSAvoidmechanical stress induction methods

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies parameter changes by modifying the lattice constant of the semiconducting material layer through dopant implantation. This changes the physical parameters of the material to induce mechanical stress, thereby enhancing charge carrier mobility and on-current without being limited by conventional stress induction methods

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality by creating doped regions specifically at the source and drain portions of the semiconducting material layer. These localized doped regions alter the lattice constant in specific areas, generating mechanical stress where needed to improve carrier mobility without affecting the entire channel uniformly

Inventive Principle:

Principle #3Local quality

2Reliability

If dopants are implanted to alter lattice constant and generate mechanical stress, then charge carrier mobility increases, but manufacturing complexity increases

Engineering Contradiction:

Improvecharge carrier mobilityVSAvoidmanufacturing process

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the stress induction function with the source and drain electrode structures. By implanting dopants into the source and drain regions of the semiconducting material layer, the patent combines the electrical contact function with the mechanical stress generation function, thereby improving carrier mobility without adding separate stress induction components

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent uses dopant atoms as intermediaries to transfer mechanical stress to the semiconducting material lattice. The implanted dopants alter the lattice constant, which then induces mechanical stress in the channel region, serving as a mediator between the implantation process and the desired stress effect

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively enhances the on-current and charge carrier mobility in TFTs by altering the lattice constant of the semiconducting material layers, leading to improved device performance and efficiency.

Implementation Method 1

metallic liners that induce compressive or tensile stress in the end portions of semiconducting material layers

Methodology Applied

Scientific EffectStress induction:

Implementation Method 2

by implanting dopants to alter the lattice constant, thereby generating mechanical stress within the channel portion

Methodology Applied

Scientific EffectLattice constant alteration:

Data Source

PatentUS20240373646A1Mobility enhancement by source and drain stress layer or implantation in thin film transistors

Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.