TFT Substrate Bottom Gate Structure 7 Mask Process
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Solution Overview
Problem
The manufacturing process of conventional low temperature poly-silicon (LTPS) thin-film transistor (TFT) substrates is complex and costly, requiring 10 masks, resulting in low product yield and high production costs due to the need for multiple patterning processes.
Innovation Solution
A simplified manufacturing method for TFT substrates using a bottom gate structure, reducing the number of masks to 7 by employing heavy and light ion doping techniques to form source and drain electrodes without the need for via holes in the interlayer dielectric layer, and using a bottom gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional top gate structure with multiple patterning processes is used, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent inverts the conventional top-gate structure to a bottom-gate structure. Instead of forming the gate electrode last (top-gate), the gate electrode is formed first at the bottom, followed by the active layer and source/drain electrodes. This inversion simplifies the manufacturing process by reducing the number of patterning steps from 10 masks to 7 masks, while maintaining manufacturing precision through the sequential layer formation approach.
2Manufacturing precision
If multiple patterning processes with 10 masks are used, then electrode positioning accuracy is improved, but productivity decreases and manufacturing cost increases
Solution Approach 1:
The patent merges multiple patterning operations into fewer steps by utilizing the bottom-gate structure. The gate electrode pattern is formed once at the bottom, and subsequent layers (active layer, source/drain electrodes) are formed using fewer additional patterning steps. This merging of operations reduces the total mask count from 10 to 7, thereby improving productivity and manufacturing throughput while maintaining adequate electrode positioning accuracy.
3Reliability
If via holes are formed in interlayer dielectric layer for electrode connection, then electrical connection is achieved, but contact resistance increases and manufacturing steps increase
Solution Approach 1:
The patent extracts the via hole formation step from the manufacturing process by adopting a bottom-gate structure. In this configuration, the gate electrode is formed at the bottom and extends to directly contact the source and drain electrodes, eliminating the need for via holes in the interlayer dielectric layer. This extraction of the via hole step reduces contact resistance and simplifies the interlayer connection structure while maintaining electrical connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces contact resistance, and significantly improves product yield and productivity by reducing the number of masks and eliminating the need for electrodes to extend through via holes, thereby lowering costs and enhancing performance.
Implementation Method 1
subjecting the photoresist pattern to dry etching treatment to reduce a thickness of the photoresist pattern
Implementation Method 2
employing heavy and light ion doping techniques to form source and drain electrodes
Data Source
AI summary
A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.