TFT Substrate with Integrated Color Filter Planarization
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Solution Overview
Problem
The manufacturing of TFT substrates for liquid crystal displays in the FFS mode requires a large number of photolithography processes, leading to increased costs and complexity.
Innovation Solution
A TFT substrate configuration and manufacturing method that reduces the number of photolithography processes by integrating a matrix of pixels with specific contact holes and conductive films, allowing for the formation of a planarization insulating film through six photolithography processes, enabling a high aperture ratio and reduced cost production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick planarization insulating film is formed above the common wirings, source wirings, and TFT elements to reduce parasitic capacitance and improve aperture ratio, then the manufacturing complexity and cost increase due to the requirement of multiple photolithography processes
Solution Approach 1:
The patent merges the planarization insulating film formation with the color filter layer formation into a single integrated structure. The color filter layer serves dual purposes: as the color filter for display and as the planarization insulating film that covers and flattens the underlying wirings and TFT elements. This eliminates the need for separate planarization film deposition and reduces the number of photolithography processes required.
Solution Approach 2:
The color filter layer is designed to perform multiple functions simultaneously: it acts as the color filter for the display, provides planarization by covering the uneven surface of underlying layers, and serves as the insulating film that reduces parasitic capacitance. This multi-functionality approach eliminates the need for dedicated separate layers for each function, thereby reducing manufacturing complexity.
2Manufacturing precision
If multiple photolithography processes are used to form the planarization insulating film and associated structures, then the aperture ratio and display quality improve, but the manufacturing cost and production time increase
Solution Approach 1:
The patent combines the formation of the color filter layer and the planarization insulating film into a single deposition and patterning process. By integrating these functions into one layer, the number of photolithography processes is reduced, thereby improving manufacturing efficiency and productivity while maintaining the required aperture ratio and display quality.
Solution Approach 2:
The color filter layer is designed and formed in advance to simultaneously serve as the planarization insulating film. This preliminary integration of functions eliminates the need for subsequent separate planarization steps, streamlining the manufacturing process and improving productivity without compromising the final aperture ratio.
3Manufacturing precision
If the pixel electrodes and signal lines are disposed apart from each other to eliminate electric field effects, then the pixel aperture ratio increases, but the device structure becomes more complex
Solution Approach 1:
The color filter layer with its specific pattern and material properties serves to self-shield the pixel electrodes from electric field effects of signal lines. The integrated structure automatically provides the necessary electrical isolation and field management through its design, eliminating the need for additional complex shielding structures or spacing arrangements.
Data Source
AI summary
A gate wiring, a source electrode, a source-electrode connecting wiring, a pixel electrode, a gate-terminal extraction electrode, and a source-terminal extraction electrode are formed in the same layer on a planarization insulating film. The gate wiring is connected to a gate electrode through a gate-electrode-portion contact hole. The source electrode is connected to a semiconductor film through a source-electrode-portion contact hole. The source-electrode connecting wiring is connected to the semiconductor film and a source wiring through the source-electrode-portion contact hole and a source-wiring-portion contact hole, respectively. The pixel electrode is connected to the semiconductor film through a drain (pixel)-electrode-portion contact hole.