TFT Substrate Composite Semiconductor for OLED

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Solution Overview

Problem

Existing thin film transistor substrates for OLED display devices face challenges with electron mobility and threshold voltage uniformity, particularly when using amorphous or oxide semiconductors, which affect display performance and require additional compensation circuits.

Innovation Solution

The design incorporates a thin film transistor substrate with a specific structure including multiple active patterns, gate electrodes, and insulation layers to form driving and switching transistors, along with a capacitor, optimized for polycrystalline and oxide semiconductor materials to enhance electron mobility and threshold voltage uniformity without the need for compensation circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the semiconductor layer is formed of amorphous semiconductor, then the manufacturing process is simpler, but the electron mobility is relatively low which is inappropriate for high speed display devices

Engineering Contradiction:
Improveease of manufactureVSAvoidelectron mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent employs a composite semiconductor layer structure combining amorphous semiconductor and crystalline semiconductor materials. The amorphous semiconductor layer provides ease of manufacture and coverage, while the crystalline semiconductor layer embedded within it delivers high electron mobility. This composite approach resolves the contradiction by integrating the advantages of both material types in a single functional layer.

Inventive Principle:
Principle #40Composite materials

2Speed

If the semiconductor layer is formed of polycrystalline semiconductor, then the electron mobility is relatively high, but the threshold voltage is not uniform due to polycrystalline nature requiring compensation circuits

Engineering Contradiction:
Improveelectron mobilityVSAvoidthreshold voltage uniformity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies local quality by creating regions with different semiconductor crystal structures within the same active layer. Specifically, certain regions contain crystalline semiconductor portions with high electron mobility, while other regions maintain amorphous structure. This spatial differentiation of material properties allows the device to achieve both high speed performance and uniform threshold voltage characteristics without requiring compensation circuits.

Inventive Principle:
Principle #3Local quality

3Reliability

If the semiconductor layer is formed of oxide semiconductor, then the threshold voltage is relatively low, but the electron mobility is lower than that of polycrystalline semiconductor

Engineering Contradiction:
Improvethreshold voltage uniformityVSAvoidelectron mobility
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent combines oxide semiconductor regions with crystalline semiconductor regions in a composite active layer structure. The oxide semiconductor portions provide low and uniform threshold voltage characteristics, while the crystalline semiconductor portions contribute high electron mobility. This composite material strategy enables the simultaneous achievement of both low threshold voltage and high speed performance.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10861920B2Thin film transistor substrate, method of manufacturing the same, and display device including the same
Publication Date: 2020.12.08 SAMSUNG DISPLAY CO LTD
  • US10861920B2 patent drawing
  • US10861920B2 patent drawing
  • US10861920B2 patent drawing

AI summary

A TFT substrate includes a first active pattern, a first gate insulation, and a first gate. A second gate is on a second gate insulation covering the first gate. A source connection electrode contacts a source region of the first active pattern. A drain connection electrode contacts its drain region. A second active pattern is on a first insulation covering the second gate. A third gate insulation covers the second active pattern. A third gate is disposed on the third gate insulation. A second insulation interlayer covers the third gate. A first source, a first drain, a second source, and a second drain are disposed on the second insulation interlayer. The first source and the first drain contact the source connection electrode and the drain connection electrode. The second source and the second drain contact a source region and a drain region of the second active pattern.