TFT Substrate Contact Hole Design for Low-Temp Deposition
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Solution Overview
Problem
In PLS mode liquid crystal displays, the high-temperature deposition of layers on a common electrode can weaken bonding strength and degrade interface properties, affecting the reliability of thin film transistors.
Innovation Solution
A thin film transistor substrate is designed with a gate insulating film having contact holes exposing common voltage lines, allowing common electrodes to be connected without direct high-temperature exposure, while maintaining bonding strength and interface properties by depositing layers at a lower temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three layers (gate insulating layer, active layer, and ohmic contact layer) are deposited on the common electrode at high temperature (350°C or higher), then the deposition process can be completed, but the bonding strength between compositions weakens and interface properties are degraded
Solution Approach 1:
The gate insulating layer, active layer, and ohmic contact layer are deposited on the substrate before the common electrode is formed. This preliminary deposition allows the layers to be formed at low temperature (280°C or lower) without exposing the common electrode to high temperature, thereby maintaining bonding strength and interface properties while completing the deposition process
Solution Approach 2:
The conventional sequence is inverted: instead of depositing layers on the common electrode, the layers are deposited on the substrate first, then the common electrode is formed. This inversion allows low-temperature deposition that preserves the common electrode's bonding strength and interface properties
2Productivity
If the common electrode is exposed to high temperature during layer deposition, then the deposition can proceed, but the bonding strength between compositions weakens
Solution Approach 1:
The gate insulating layer, active layer, and ohmic contact layer are deposited on the substrate before the common electrode is formed, allowing the deposition to proceed at low temperature (280°C or lower) without exposing the common electrode to high temperature, thereby maintaining bonding strength between compositions
3Strength
If layers are deposited at low temperature (280°C or lower) to prevent bonding strength weakening, then bonding strength is maintained, but interface properties are remarkably degraded
Solution Approach 1:
The gate insulating layer, active layer, and ohmic contact layer are deposited on the substrate before the common electrode is formed. This preliminary deposition at low temperature (280°C or lower) maintains bonding strength while the subsequent formation of the common electrode at higher temperature ensures proper interface properties without damaging the previously deposited layers
Data Source
AI summary
This invention relates to a thin film transistor substrate, a method of manufacturing the same, and a liquid crystal display panel including the same. The thin film transistor substrate includes a substrate, gate lines disposed on the substrate and extending in one direction, common voltage lines disposed on the substrate and spaced apart from the gate lines, and a gate insulating film disposed on the gate lines and the common voltage lines, the gate insulating film having first contact holes exposing a part of each common voltage line. Common electrodes are disposed on the gate insulating film and are connected to the common voltage lines through the first contact holes. Data lines are disposed on the gate insulating film and extend in a direction crossing the gate lines and thin film transistors are disposed at crossings of the gate lines and the data lines. The thin film transistors are connected to the gate lines and the data lines and include source electrodes and drain electrodes. Pixel electrodes are connected to the thin film transistors.