Thin Film Transistor Substrate Manufacturing with Dual Doping
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Solution Overview
Problem
Existing methods for manufacturing thin film transistor substrates for organic light-emitting display apparatuses face challenges in efficiently forming semiconductor patterns and doping processes, which affect the performance and off-current characteristics of thin film transistors.
Innovation Solution
A method involving the formation of a semiconductor pattern on a substrate, followed by sequential doping with high-concentration and low-concentration impurities using photosensitive patterns, and the creation of dual gate electrodes to form a lightly-doped drain (LDD) area, reducing off-current and improving resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping processes are used to form semiconductor patterns, then the manufacturing process is simple, but the off-current characteristics deteriorate
Solution Approach 1:
The doping process is segmented into multiple stages: first doping to form the semiconductor pattern with initial impurity concentration, and second doping to adjust impurity concentration in specific regions. This segmentation allows precise control of off-current characteristics while maintaining manufacturing feasibility.
Solution Approach 2:
Different impurity concentrations are applied to different regions of the semiconductor pattern. The second doping process specifically targets regions requiring lower impurity concentration to reduce off-current, while preserving higher concentration regions for optimal device performance.
2Reliability
If multiple doping steps are performed to improve transistor performance, then off-current is reduced, but the manufacturing time increases
Solution Approach 1:
The first doping process is performed preliminarily to establish the basic semiconductor pattern with appropriate impurity concentration. This preliminary action creates a foundation that reduces the complexity and time required for subsequent second doping steps to achieve final performance optimization.
Solution Approach 2:
Multiple doping operations are merged into a coordinated sequence where first doping and second doping are integrated with gate electrode formation and photosensitive pattern processing. This merging allows simultaneous achievement of performance optimization and manufacturing efficiency.
3Reliability
If high impurity concentration is used in semiconductor patterns, then conductivity is improved, but off-current increases
Solution Approach 1:
The patent applies different impurity concentrations to different spatial regions of the semiconductor pattern. Regions requiring low off-current are doped with lower impurity concentration in the second doping step, while other regions maintain higher concentration for conductivity, achieving local optimization of both parameters.
Solution Approach 2:
The impurity concentration parameter is dynamically adjusted through sequential doping processes. The second doping step modifies the impurity concentration parameter in specific regions to reduce off-current, while the first doping step establishes the baseline concentration for overall conductivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of thin film transistors by reducing off-current and enabling high-resolution organic light-emitting display apparatuses with simplified impurity implantation processes.
Implementation Method 1
forming a first photosensitive pattern, wherein the first photosensitive pattern includes a first thickness
Implementation Method 2
doping the semiconductor pattern with first impurities using the first photosensitive pattern
Data Source
AI summary
A method of manufacturing a thin film transistor substrate includes forming a semiconductor pattern on a substrate, wherein the semiconductor pattern includes a first area, a second area, and a third area, wherein the second area and the third area are located on each side of the first area; forming an insulating layer on the substrate to cover the semiconductor pattern; forming a metal pattern layer on the insulating layer using a first photosensitive pattern; doping the semiconductor pattern with first impurities using the first photosensitive pattern; forming a gate electrode by patterning the metal pattern layer using a second photosensitive pattern; and doping the semiconductor pattern with second impurities having a lower concentration than the first impurities.