TFT Substrate Dual Layer Source Wire Design
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Solution Overview
Problem
The challenge in manufacturing thin film transistor (TFT) substrates is the difficulty in selective etching of oxide semiconductor films without affecting metal electrodes, leading to increased interface resistance and degraded on-off characteristics due to interface reactions between oxide semiconductor films and metal electrodes.
Innovation Solution
A TFT substrate design with a dual layer source wire structure and upper-layer source/drain electrodes connected through contact holes, increasing the contact area with the semiconductor film and reducing interface resistance, while also allowing for compensation of high interface resistance at one interface with the other, preventing defects from poor wire patterns or broken wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If oxide semiconductor films are directly formed on metal electrodes by sputtering or vacuum evaporation, then the manufacturing process is simple, but interface resistance increases due to oxide layer formation at the interface
Solution Approach 1:
The patent introduces an intermediary layer (such as a buffer layer or intermediate metal layer) between the oxide semiconductor film and the metal electrode. This intermediary layer prevents direct contact between the oxide semiconductor and reactive metal, thereby preventing oxide layer formation at the interface while maintaining manufacturing simplicity through standard deposition processes.
Solution Approach 2:
The patent applies preliminary surface treatment or modification to the metal electrode before forming the oxide semiconductor film. This preliminary action creates a surface condition that prevents oxide formation during subsequent deposition, resolving the contradiction by preparing the interface in advance to avoid the harmful oxide layer.
2Manufacturing precision
If selective etching is performed to remove only metal films while leaving oxide semiconductor, then etching selectivity is achieved, but the process becomes complex and difficult to control
Solution Approach 1:
The patent applies different etching-resistant properties to different regions of the structure by using localized protective layers or modifying the etching solution composition locally. This allows selective removal of metal films while preserving oxide semiconductor through controlled local quality differences rather than complex global process control.
Solution Approach 2:
The patent uses composite material structures where the metal electrode is combined with etching-resistant materials or the oxide semiconductor is combined with etching-enhancing materials. This composite approach enables selective etching through material composition differences rather than complex process parameters.
3Reliability
If contact area between electrodes and semiconductor film is increased, then interface resistance is reduced, but device structure becomes more complex
Solution Approach 1:
The patent increases the contact area by transitioning from planar contact to three-dimensional contact structures, such as forming electrodes that wrap around the semiconductor film or creating vertically stacked contact regions. This dimensional change achieves larger contact area without proportionally increasing planar device footprint or structural complexity.
Solution Approach 2:
The patent implements nested contact structures where one electrode layer is positioned within or around another layer, creating multiple contact interfaces in a compact configuration. This nesting approach increases total contact area while maintaining compact device structure and avoiding excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a high-performance TFT substrate with improved mobility and yield, enabling the production of high-quality liquid crystal display devices with reduced interface resistance and enhanced reliability.
Implementation Method 1
an oxide layer of a metal film is formed at an interface therebetween due to an interface reaction, which increases an electrical resistance (interface resistance)
Implementation Method 2
formed on a metal film (Cr, Ti, Cu, Mo, Ta, Al, and alloys thereof) that is used for a source electrode and a drain electrode of a TFT by a well-known sputtering process or vacuum evaporation process
Implementation Method 3
formed on a metal film (Cr, Ti, Cu, Mo, Ta, Al, and alloys thereof) that is used for a source electrode and a drain electrode of a TFT by a well-known sputtering process or vacuum evaporation process
Data Source
AI summary
A thin film transistor substrate includes a thin film transistor, a source wire, an upper-layer source wire, and a pixel electrode. The thin film transistor includes: a source electrode and a drain electrode located to be spaced from each other on the same plane; a semiconductor film located to straddle those electrodes; an insulating film located to cover at least the source electrode, the drain electrode, and the semiconductor film; an upper-layer source electrode and an upper-layer drain electrode located on the insulating film and respectively connected to the semiconductor film through contact holes; and a gate electrode located below or above the semiconductor film. The source wire extends from the source electrode. The upper-layer source wire extends from the upper-layer source electrode. The pixel electrode is electrically connected to the drain electrode.