TFT Array Substrate Layout for Lower Gate-Source Parasitics
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Solution Overview
Problem
Existing TFT array substrates face issues with parasitic capacitance and parasitic voltage due to overlapping areas between the gate and the source/drain, which affect the conductivity and performance of thin-film transistors, especially in double-gate structures where the buffer layer fails to prevent these issues.
Innovation Solution
A TFT array substrate design featuring a protrusive structure between the source and drain with a top gate positioned inside, minimizing the overlapped area with the gate, thereby controlling parasitic capacitance and voltage, and suitable for both single and double-gate configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate area is increased to improve transistor conductivity, then the conductivity is improved, but the parasitic capacitance and parasitic voltage increase due to larger overlapping area with source and drain
Solution Approach 1:
The patent introduces a protrusive structure that extends in the vertical dimension, allowing the gate to be positioned above the source and drain regions. This spatial separation in the vertical dimension reduces the planar overlapping area between the gate and source/drain, thereby reducing parasitic capacitance while maintaining effective gate control over the channel.
Solution Approach 2:
The gate is nested within the protrusive structure, which is formed between the source and drain regions. This nesting arrangement allows the gate to be positioned in a dedicated space above the channel, minimizing overlap with source and drain while maintaining effective electrical control over the active layer channel.
2Object-generated harmful factors
If the overlapping area between gate and source/drain is reduced to minimize parasitic capacitance, then parasitic capacitance is reduced, but the gate area may become insufficient for effective control
Solution Approach 1:
By utilizing the vertical dimension through the protrusive structure, the gate achieves effective control over the channel without requiring large planar overlap with source and drain. The gate's position above the channel in the vertical dimension provides sufficient electrostatic control while minimizing harmful parasitic effects.
Solution Approach 2:
The protrusive structure creates a localized region with different spatial characteristics, concentrating the gate's electrical influence directly over the channel area where control is needed, while reducing influence over source and drain regions where parasitic effects are harmful.
3Ease of manufacture
If a conventional flat gate structure is used, then the manufacturing process is simple, but parasitic capacitance cannot be effectively controlled
Solution Approach 1:
The gate structure is segmented into a distinct protrusive portion that separates the gate from the source and drain regions. This segmentation is achieved through patterned etching and deposition processes that create the protrusive structure, allowing the gate to be formed in a dedicated space above the channel.
Solution Approach 2:
The manufacturing process incorporates vertical dimensionality by forming the protrusive structure through controlled etching and filling operations. This creates a three-dimensional gate configuration that reduces parasitic capacitance while using standard semiconductor fabrication techniques.
Data Source
AI summary
A thin-film transistor (TFT) array substrate, a preparation method thereof, and a display device are provided. The TFT array substrate includes a source, a drain, and a first gate; wherein a protrusive structure is defined between the source and the drain, and the first gate is disposed inside the protrusive structure; and in a plane where a surface of the first gate is disposed, a sum of an overlapped area of a projection of the source and a projection of the first gate and an overlapped area of a projection of the drain and the projection of the first gate is less than an area threshold.