TFT Substrate Gray Tone Mask Single Photolithography Process
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Solution Overview
Problem
The manufacturing process of thin-film transistor (TFT) substrates for active matrix organic light emitting diodes (AMOLEDs) is complex, requiring ten photolithographic processes, which affects efficiency and yield rate.
Innovation Solution
A method involving a gray tone mask to simultaneously pattern a gate insulation layer, semiconductor layer, and etch stop layer using a single photolithographic process, reducing the number of processes from ten to eight and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic processes are used to pattern each layer separately, then manufacturing precision is maintained, but device complexity and manufacturing time increase significantly
Solution Approach 1:
The patent combines the patterning of gate insulation layer, semiconductor layer, and etch stop layer into a single photolithographic process using a multi-layer photoresist structure. The first photoresist layer patterns the gate insulation layer and semiconductor layer, while the second photoresist layer patterns the etch stop layer, both simultaneously in one exposure and development cycle, thereby reducing process complexity while maintaining precision
Solution Approach 2:
The photoresist structure serves multiple functions: the first photoresist layer acts as both the patterning layer for gate/semiconductor structures and as an etch stop layer for the second photoresist layer. The second photoresist layer patterns the etch stop layer while being protected by the first layer. This multi-functional design reduces the number of separate photolithographic processes needed
2Manufacturing precision
If multiple photolithographic processes are used for each layer, then manufacturing precision is ensured, but productivity decreases due to increased process steps
Solution Approach 1:
The patent merges multiple photolithographic patterning operations into a single process by using a multi-layer photoresist system. Both the gate insulation layer/semiconductor layer and the etch stop layer are patterned simultaneously in one exposure and development cycle, significantly improving manufacturing efficiency while maintaining precise pattern alignment through the layered photoresist structure
Solution Approach 2:
The first photoresist layer is applied and patterned first to define the gate insulation layer and semiconductor layer patterns. This preliminary patterning creates a protective structure that guides the subsequent patterning of the etch stop layer through the second photoresist layer, ensuring precise alignment without requiring separate photolithographic processes
3Manufacturing precision
If separate photolithographic processes are used for each layer, then manufacturing precision is maintained, but loss of time increases due to multiple process steps
Solution Approach 1:
The patent combines the patterning of multiple layers (gate insulation layer, semiconductor layer, and etch stop layer) into a single photolithographic process. The multi-layer photoresist structure enables simultaneous pattern definition for all layers in one exposure and development cycle, reducing manufacturing cycle time while maintaining precise layer definition through the structured photoresist arrangement
Data Source
AI summary
A TFT substrate includes a base plate on which first and second gate electrodes respectively corresponding to first and second TFTs are formed. A gate insulation layer, a semiconductor layer, and an etch stop layer are sequentially formed on the base plate and the first and second electrodes. A single photolithographic process is conducted simultaneously on the gate insulation layer, the semiconductor layer, and the etch stop layer with the same gray tone mask to form separate semiconductor portions for the two TFTs and also form contact holes in the etch stop layer and the gate insulation layer to receive sources and drains of the two TFTs to be deposited therein and in contact with the two semiconductor portions.