TFT Substrate Inorganic Barrier Layer Parasitic Capacitance
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Solution Overview
Problem
Existing thin film transistor (TFT) technologies face challenges in minimizing parasitic capacitance and protecting the active semiconductor layer during manufacturing, leading to reduced reliability and increased size due to overlapping electrode structures and direct contact with planarization layers.
Innovation Solution
The implementation of a TFT substrate with an inorganic barrier layer that prevents direct contact between the planarization layer and the active pattern, using a specific etch-stop layer pattern and electrode configuration to minimize overlapping areas and reduce parasitic capacitance, and employing an oxide semiconductor with a metal oxide or silicon oxide inorganic barrier layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source and drain electrodes are superimposed over both ends of the gate electrode, then electrical connection is improved, but parasitic capacitance increases
Solution Approach 1:
An inorganic barrier layer is introduced as an intermediary between the planarization layer and the active pattern. This barrier layer prevents direct contact while maintaining the electrode configuration, thereby reducing parasitic capacitance without compromising electrical connection reliability
Solution Approach 2:
The etch-stop layer pattern is configured with different regions (central portion and peripheral portion) that have different functions. The peripheral portion allows electrode contact while the central portion prevents excessive overlapping, locally optimizing the balance between electrical connection and parasitic capacitance reduction
2Ease of manufacture
If planarization layer is formed directly on source and drain electrodes, then manufacturing simplicity is improved, but active semiconductor modification and outgassing occur
Solution Approach 1:
The inorganic barrier layer serves as a protective intermediary between the planarization layer and the active pattern. It prevents harmful interactions such as modification and outgassing while allowing the planarization process to proceed, thus maintaining manufacturing simplicity without compromising semiconductor stability
Solution Approach 2:
The inorganic barrier layer is formed beforehand to prevent potential damage from the planarization layer. This preemptive protective measure cushions the active pattern against modification and outgassing that would otherwise occur during planarization
3Manufacturing precision
If etch-stop layer pattern completely covers active pattern, then manufacturing precision is improved, but TFT size increases
Solution Approach 1:
The etch-stop layer pattern is selectively configured with central and peripheral portions that serve different purposes. The peripheral portion extends for manufacturing precision while the central portion is reduced, achieving pattern alignment accuracy without excessive TFT size increase
Solution Approach 2:
The etch-stop layer pattern is divided into functional segments (central portion and peripheral portion) that can be independently optimized. This segmentation allows the peripheral portion to provide alignment precision while the overall structure maintains compact dimensions
Data Source
AI summary
A thin film transistor substrate may include a gate electrode on a base substrate, a gate insulation layer covering the gate electrode on the base substrate, an active pattern on the gate insulation layer, an etch-stop layer pattern partially exposing the active pattern, a source electrode and a drain electrode in contact with a portion of the exposed active pattern, and an inorganic barrier layer on the source electrode, the drain electrode, and the etch-stop layer pattern. The active pattern may be superimposed over the gate electrode. The source electrode and the drain electrode may be superimposed over both ends of the gate electrode. The inorganic barrier layer may be in contact with a remaining portion of the exposed active pattern.