TFT Array Substrate Structure for Protecting Semiconductor Layers
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Solution Overview
Problem
Existing thin film transistor technologies face challenges in maintaining semiconductor layer integrity during gate insulator etching, leading to potential damage, loss, or non-uniformity, which affects electrical characteristics and mobility, and also result in parasitic capacitance and thickness issues in display devices.
Innovation Solution
A thin film transistor array substrate structure is designed with a semiconductor layer having distinct conductorization portions and a gate insulator layer with contact holes, where the gate insulator layer is not etched between the source and drain contact regions, and a functional insulating layer is used to differentiate conductivity and prevent semiconductor layer damage, while also forming a capacitor with reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the gate insulator layer is etched for various reasons, then access to conductorization portions is enabled, but the semiconductor layer may be lost, damaged, or cut off during the etching process
Solution Approach 1:
The patent introduces an intermediate protective structure where the gate insulator layer is selectively retained in regions between the source and drain contact regions. This intermediate layer acts as a mediator that protects the semiconductor layer during etching operations while still allowing access to the conductorization portions through controlled etching of other areas.
Solution Approach 2:
The gate insulator layer is segmented into different regions: some areas are etched away to provide access to conductorization portions, while other areas are retained to protect the semiconductor layer. This segmentation allows simultaneous achievement of electrical access and structural protection.
2Productivity
If amorphous silicon is used as the active layer, then manufacturing process time is short and production cost is low, but current driving capability is relatively low due to low mobility
Solution Approach 1:
The patent modifies the physical and chemical parameters of the amorphous silicon layer through controlled etching and protective layer formation, enhancing its electrical properties without changing the fundamental material composition. This allows maintaining the manufacturing advantages of amorphous silicon while improving mobility and current driving capability.
3Speed
If oxide semiconductor is used as the active layer, then mobility is high and transparency is achieved, but a separate conductorization process is required to form connection portions
Solution Approach 1:
The patent combines the gate insulator layer formation and conductorization process into a single integrated structure. The gate insulator layer serves dual functions as both the insulating layer and the protective conductorization portion, eliminating the need for separate conductorization processes while maintaining high mobility characteristics of oxide semiconductors.
4Ease of operation
If the gate insulator layer is etched completely, then contact to conductorization portions is achieved, but parasitic capacitance increases and capacitor thickness is increased
Solution Approach 1:
The patent extracts only the necessary portions of the gate insulator layer for electrical contact while retaining the majority of the layer to maintain capacitor structure integrity. This selective removal reduces parasitic capacitance and maintains thin capacitor design while still providing adequate contact to conductorization portions.
Data Source
AI summary
Embodiments of the present disclosure relate to a thin film transistor array substrate and display device in which a semiconductor layer has a heterogeneous conductorization structure including heterogeneous conductorization portions having different electrical conductivity, and the gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode part and the gate electrode part and between the drain electrode part and the gate electrode part, so that the possibility of damage to the semiconductor layer can be eliminated or reduced.