TFT Substrate Fabrication via Merged Photolithography
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Solution Overview
Problem
The existing methods for fabricating thin-film transistor (TFT) substrates, such as the 4-mask process, are complex and do not adequately reduce manufacturing time and cost, as they involve multiple processes and can lead to defects.
Innovation Solution
A TFT substrate is fabricated using an insulating substrate with gate wiring, semiconductor patterns, data wiring, and a passivation layer comprising multiple sub-layers with varying densities, and a method involving the disposition of gate wiring, semiconductor patterns, data wiring, and a passivation layer, followed by etching and reflow processes to form pixel electrodes, which simplifies the process and reduces defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography with multiple masks is used to dispose wiring on TFT substrate, then wiring precision and alignment are improved, but processing time and manufacturing cost increase
Solution Approach 1:
The patent combines multiple photolithography processes into a single integrated process. The method performs gate wiring formation, data wiring formation, and pixel electrode formation in one continuous operation without requiring multiple separate mask alignment steps, thereby reducing processing time while maintaining wiring precision through the unified process design
Solution Approach 2:
The photolithography process is designed to perform multiple functions simultaneously: it forms gate wiring, data wiring, and pixel electrodes in a single process step. This multi-functional approach eliminates the need for separate dedicated processes for each wiring type, reducing overall processing time while maintaining the precision required for all wiring structures
2Manufacturing precision
If photolithography with multiple masks is used to dispose wiring on TFT substrate, then wiring precision and alignment are improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple photolithography processes into one integrated process, eliminating the need for multiple mask purchases, multiple alignment systems, and repeated process setup. This consolidation significantly reduces manufacturing cost while maintaining wiring precision through the unified process design that handles gate wiring, data wiring, and pixel electrode formation simultaneously
Solution Approach 2:
The photolithography process is designed with universal capability to form all wiring structures (gate wiring, data wiring) and pixel electrodes in a single operation. This multi-functionality eliminates the need for multiple specialized processes, reducing equipment investment, material costs, and operational expenses while maintaining the precision required for all wiring types
3Ease of manufacture
If 4-mask process is used instead of 5-mask process, then manufacturing cost is reduced, but process complexity remains high
Solution Approach 1:
The patent merges the functions of multiple masks into a single integrated photolithography process. Instead of using 4 or 5 separate masks for different wiring layers, the method uses one process to form all wiring structures and pixel electrodes, eliminating mask-related complexity while maintaining cost efficiency through process simplification
Solution Approach 2:
The patent extracts and eliminates the mask process entirely from the manufacturing sequence. By replacing the multi-mask photolithography approach with a direct imaging or single-step patterning method, the process complexity associated with mask alignment, mask fabrication, and multiple exposure steps is removed, while manufacturing cost is reduced through fewer process steps
4Manufacturing precision
If multiple photolithography processes are used, then wiring formation precision is improved, but the number of processes increases
Solution Approach 1:
The patent combines multiple separate photolithography processes into one integrated process. The method forms gate wiring, data wiring, and pixel electrodes in a single continuous operation, reducing the total number of processes while maintaining wiring formation precision through the unified process design that controls all patterning steps simultaneously
Solution Approach 2:
The photolithography process is designed with universal capability to form all wiring structures and pixel electrodes in a single operation. This multi-functional approach eliminates the need for multiple dedicated patterning processes, reducing process complexity while maintaining the precision required for all wiring formations through the integrated process control
Data Source
AI summary
A thin-film transistor (“TFT”) substrate and a method of fabricating the same include: an insulating substrate; gate wiring which is disposed on the insulating substrate and includes a gate line and a gate electrode; a semiconductor pattern which is disposed on the gate electrode; data wiring which is disposed on the semiconductor pattern and includes a data line, a source electrode, and a drain electrode; a passivation layer which includes a first sub-passivation layer and a second sub-passivation layer deposited on the data wiring; and a pixel electrode which is electrically connected to the drain electrode through a contact hole disposed in the passivation layer, wherein the second sub-passivation layer has a lower density than the first sub-passivation layer.