TFT Array Substrate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing thin film transistor array substrates in organic light-emitting displays face issues with parasitic capacitance and leakage currents, which affect the performance and reliability of large-sized and high-resolution displays.
Innovation Solution
The use of a thin film transistor structure with a silicon active layer and an oxide active layer, where regions not overlapping the gate electrode are doped with N+ or P+ ion impurities, and the source and drain electrodes are formed without overlapping the gate electrode, reducing parasitic capacitance and increasing conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source and drain electrodes are formed to overlap the gate electrode, then electrical connection is ensured, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful overlap region between source/drain electrodes and gate electrode by introducing a bridge electrode structure. The source and drain electrodes are separated and connected through a bridge electrode that extends from the source electrode toward the gate electrode but maintains a gap, thereby eliminating direct overlap and reducing parasitic capacitance while preserving electrical connection functionality.
Solution Approach 2:
The bridge electrode serves as an intermediary element between the source electrode and the gate electrode. It provides an indirect connection path that avoids direct contact between the source/drain electrodes and the gate electrode, thereby reducing parasitic capacitance while maintaining the necessary electrical connection for device operation.
2Reliability
If ion impurities are doped in regions overlapping the gate electrode, then conductivity is improved, but parasitic capacitance and leakage current increase
Solution Approach 1:
The patent applies local quality by selectively doping ion impurities only in specific regions that do not overlap with the gate electrode. The doping is concentrated in the source and drain electrode regions away from the gate overlap area, providing high conductivity where needed while avoiding the creation of parasitic capacitance and leakage paths in the overlap region.
Solution Approach 2:
The active layer is segmented into different functional regions with distinct doping characteristics. Regions under the gate electrode remain undoped or lightly doped to minimize parasitic effects, while source and drain regions are heavily doped for high conductivity. This segmentation allows optimization of each region's properties independently.
3Ease of manufacture
If a single silicon active layer is used, then manufacturing is simple, but parasitic capacitance and leakage current are high
Solution Approach 1:
The patent employs a composite active layer structure consisting of multiple silicon layers with different doping concentrations and characteristics. This composite structure combines the advantages of different silicon layers to achieve low parasitic capacitance and low off-state leakage current while maintaining manufacturability through established multi-layer deposition and doping techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure decreases parasitic capacitance and off-state leakage current while increasing on-state current, enhancing the performance and reliability of large-sized and high-resolution organic light-emitting displays.
Implementation Method 1
Regions of the first silicon active layer and the second silicon active layer that do not overlap the gate electrode may be doped with N+ or P+ ion impurities.
Data Source
AI summary
Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.