TFT Substrate Peripheral Wiring via Multi-Layer Stacking
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Solution Overview
Problem
Current liquid crystal display (LCD) technologies face challenges in increasing pixels per inch (PPI) while maintaining low power consumption and electrostatic discharge resistance, as increasing the number of gate driver-on-array (GOA) circuit stages within the panel raises product costs and reduces the capability of peripheral wiring to resist electrostatic discharge.
Innovation Solution
A thin-film transistor (TFT) substrate design featuring a backing plate with multiple insulation and metal layers, including vias in the second insulation layer to connect peripheral signal wiring traces with a third metal layer, reducing electrical resistance and improving electrostatic discharge resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of GOA circuit stages is increased to increase PPI, then the pixels per inch is improved, but the product cost increases and the capability of peripheral wiring for resisting electrostatic discharge is reduced
Solution Approach 1:
The patent introduces a multi-layer metal structure with vias connecting different layers, transitioning from a single-plane wiring layout to a three-dimensional stacked architecture. This dimensional change allows signal routing in multiple layers, reducing the burden on peripheral wiring and enabling higher PPI without proportionally increasing peripheral wiring complexity or cost.
Solution Approach 2:
The patent divides the wiring function across multiple metal layers (second metal layer for peripheral signal wiring, third metal layer for additional routing), with vias providing vertical connections. This segmentation of wiring functions across layers reduces the complexity of any single layer and allows independent optimization of each layer's routing.
2Length of moving object
If the distance of glass cutting edge within the wire laying zone is reduced to make the panel thinner, then the device body thickness is improved, but the capability of peripheral wiring for resisting electrostatic discharge is reduced
Solution Approach 1:
The patent uses multiple stacked metal layers with vias to create vertical routing paths, moving electrostatic discharge protection functions from the horizontal plane to the vertical dimension. This allows the glass cutting edge distance to be reduced for thinner panels while maintaining ESD resistance through the multi-layer structure.
Solution Approach 2:
The patent introduces a dedicated third metal layer that acts as an intermediary for electrostatic discharge protection, separate from the second metal layer's signal wiring. This intermediary layer provides specialized ESD protection pathways without interfering with signal routing, maintaining reliability while enabling thinner design.
3Length of moving object
If the peripheral wiring capability for resisting electrostatic discharge is reduced, then the device can be made thinner, but the power consumption of control ICs increases
Solution Approach 1:
The patent employs vertical vias and multi-layer stacking to reduce horizontal wiring distances and improve signal integrity. This dimensional transition reduces signal attenuation and reflection, lowering the power consumption of control ICs while enabling thinner device design.
Solution Approach 2:
The patent combines signal wiring and electrostatic discharge protection functions into an integrated multi-layer structure, where the third metal layer serves both as additional signal routing and as ESD protection. This merging eliminates the need for separate dedicated ESD structures, reducing overall device thickness while maintaining low power consumption.
Data Source
AI summary
A TFT substrate and a manufacturing method thereof are provided. The TFT substrate includes a plurality of vias formed in a second insulation layer that is formed on a second metal layer that forms peripheral signal wiring traces of the TFT substrate so as to line up in an extension direction of each of the peripheral signal wiring traces and a third metal layer that is formed on the second insulation layer at a location corresponding to each of the peripheral signal wiring traces such that the third metal layer is connected, through the vias, with each of the peripheral signal wiring traces to thereby reduce the electrical resistance of each of the peripheral signal wiring traces and thus lowering down power consumption of control ICs and improving capability of the TFT substrate for resisting electrostatic discharge.