TFT Substrate Same-Layer Electrode Integration

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Solution Overview

Problem

The existing TFT substrate manufacturing process is overly complex due to the requirement of multiple mask processes, which complicates the formation of various layers and electrodes, particularly in flexible display applications where polymer materials like polyimide are used.

Innovation Solution

The proposed TFT substrate design simplifies the manufacturing process by reducing the number of mask processes through a novel layer configuration where the source and drain electrodes are formed on the same layer, overlapping the blocking layer, and using a hydrogen-containing interlayer dielectric for reduced thermal treatment steps, thereby integrating the formation of the first and second connection electrodes with the gate electrodes on the same layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple mask processes are used to form various layers and electrodes, then the TFT substrate can be manufactured with proper layer structure, but the manufacturing process becomes overly complex

Engineering Contradiction:
Improvelayer structure formationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the formation of source and drain electrodes into a single layer structure, where they are formed simultaneously in the same processing step rather than requiring separate mask processes. This combining of electrode formation operations directly reduces manufacturing process complexity while maintaining the required layer structure precision

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interlayer dielectric layer is designed to serve multiple functions: it provides electrical insulation between different electrode layers, contains hydrogen for thermal treatment of the active layer, and structurally supports the connection between various electrodes. This multi-functionality reduces the need for additional dedicated layers and processing steps

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple mask processes are used to form connection electrodes, then proper electrical connections can be achieved, but the number of mask processes increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidnumber of mask processes
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The first and second connection electrodes are formed in the same processing step as the gate electrodes, merging multiple electrode formation operations into a single mask process. This ensures proper electrical connections are achieved while significantly reducing the total number of mask processes required

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The connection electrodes are formed preliminarily during the gate electrode formation step, before subsequent processing steps. This preliminary formation of connection paths eliminates the need for later separate mask processes to create these essential electrical connections

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9842864B2Thin film transistor substrate and display apparatus using the same
Publication Date: 2017.12.12 LG DISPLAY CO LTD
  • US9842864B2 patent drawing
  • US9842864B2 patent drawing
  • US9842864B2 patent drawing

AI summary

A thin film transistor (TFT) substrate is disclosed. The TFT substrate includes a substrate, a blocking layer, a source electrode, and a drain electrode on a same layer over the substrate, an active layer overlapping the blocking layer, the source electrode, and the drain electrode, a gate insulation layer over the active layer, a first gate electrode over the gate insulation layer, an interlayer dielectric over the first gate electrode, a first connection electrode over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole, a second connection electrode over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole, a planarization layer over the first connection electrode and the second connection electrode, and a pixel electrode over the planarization layer and connected to the second connection electrode through a third contact hole.