TFT Array Substrate Cutoff Layout for Uniform OLED Scan-Line Load

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Solution Overview

Problem

Large and high-resolution organic EL display devices face issues with signal delay and distortion due to uneven driving load on wirings, leading to decreased display quality, as parasitic capacitance and resistance cause differences in signal delay and image distortion between the edge and central portions of the screen.

Innovation Solution

The implementation of a display device structure with a cutoff region that intersects specific rows and columns, where a semiconductor film or metal film is placed to adjust the driving load on scanning lines, ensuring uniform signal delivery and reducing luminance unevenness by adding adjustment capacitance to match the load of other scanning lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the display device size and resolution are increased, then the display quality is improved, but the signal delay and distortion increase due to uneven driving load on wirings

Engineering Contradiction:
Improvedisplay qualityVSAvoidsignal delay and distortion
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies local quality by forming a semiconductor film or metal film at specific locations (cutoff regions) where scanning lines intersect with non-display regions. This localized structure adds adjustment capacitance only to scanning lines that require load balancing, rather than uniformly modifying all scanning lines. The semiconductor film is positioned to overlap with specific scanning lines in the cutoff region, creating location-dependent capacitance adjustments that compensate for the uneven driving load caused by large display size and high resolution.

Inventive Principle:
Principle #3Local quality

2Reliability

If a semiconductor film or metal film is added to adjust driving load, then signal delay and distortion are reduced, but the device complexity increases

Engineering Contradiction:
Improvesignal delay and distortionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the adjustment capacitance function with existing cutoff structures. The semiconductor film or metal film is formed in the cutoff region, which is already a necessary structural element for defining display boundaries and routing wirings. By placing the adjustment capacitance in the same cutoff region, the patent combines two functions (display boundary definition and signal load adjustment) into a single integrated structure, avoiding the need for separate capacitance components and reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The cutoff region serves multiple functions: it defines the boundary of the display region, provides routing paths for scanning lines and signal lines, and now also serves as the location for adjusting driving load through the semiconductor or metal film. This multi-functional use of the cutoff region eliminates the need for dedicated adjustment structures, thereby reducing device complexity while achieving signal delay and distortion compensation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If adjustment capacitance is added to scanning lines, then luminance uniformity is improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveluminance uniformityVSAvoidmanufacturing process
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The semiconductor film or metal film is formed during the early stages of the manufacturing process, before the light-emitting elements and other pixel components are assembled. The cutoff region and adjustment film are created as part of the substrate preparation process, allowing subsequent layers and components to be built upon this pre-configured structure. This preliminary formation of the adjustment capacitance simplifies the overall manufacturing flow by integrating it into existing process steps rather than requiring additional post-assembly operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11810925B2TFT array substrate
Publication Date: 2023.11.07 MAGNOLIA WHITE CORP
  • US11810925B2 patent drawing
  • US11810925B2 patent drawing
  • US11810925B2 patent drawing

AI summary

A display device includes a plurality of pixels, first to nth scanning lines, and a first semiconductor film. The plurality of pixels is arranged in first to nth rows and first to mth columns. The first to nth scanning lines are electrically connected to the pixels in the respective first to nth rows. The first semiconductor film overlaps with at least one of first to kth scanning lines. A display region has a cutoff intersecting the first to nth rows, and the first semiconductor film is located in the cutoff. Each of the plurality of pixels includes a light-emitting element (OLED) and a transistor electrically connected to the OLED and having a second semiconductor film. The first semiconductor film and the second semiconductor film exist in the same layer. n and m are each a natural number larger than 1, and k is a natural number smaller than n.