TFT Substrate With Three Parallel Storage Capacitors
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Solution Overview
Problem
Conventional AM-OLED devices face challenges in increasing storage capacitance while maintaining aperture ratio and displaying performance, as expanding storage capacitors either reduces aperture ratio or poses a risk of damage.
Innovation Solution
A method for manufacturing a TFT substrate with three parallel-connected storage capacitors, comprising a first, second, and third storage capacitor formed using specific metal and oxide semiconductor layers, with interposed insulation and etch stop layers, to increase storage capacitance within a reduced area, enhancing aperture ratio and displaying performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the surface area of storage capacitor electrode plates is expanded, then the storage capacitance is increased, but the area of the aperture zone is reduced, leading to reduced aperture ratio and displaying brightness
Solution Approach 1:
The patent transitions from a conventional single-capacitor layout to a three-dimensional stacked configuration with three storage capacitors (C11, C12, C13) positioned at different vertical levels. This dimensional change allows the capacitors to occupy different spatial zones, increasing total storage capacitance without proportionally increasing the planar footprint, thereby preserving aperture ratio.
Solution Approach 2:
The patent implements a nested structure where multiple storage capacitors are integrated within a compact region. The first, second, and third storage capacitors are arranged such that their electrode plates and insulation layers are interlaced vertically, with each capacitor nested within the same horizontal footprint area, maximizing space utilization.
2Quantity of substance
If the distance between two storage capacitor electrode plates is reduced, then the storage capacitance is increased, but there is a risk of breaking through, leading to potential damage to the AM-OLED
Solution Approach 1:
Instead of reducing the distance between plates in a single capacitor, the patent distributes three capacitors across different vertical dimensions. Each capacitor maintains adequate plate spacing for reliability, while the combination of three capacitors achieves the required total capacitance through additive effect rather than extreme miniaturization of individual components.
Solution Approach 2:
The patent divides the storage capacitance requirement into three separate capacitors (C11, C12, C13) rather than relying on a single large capacitor. This segmentation allows each individual capacitor to have sufficient electrode plate spacing for reliability, while the cumulative capacitance of all three meets the display performance requirements.
3Stability of the object's composition
If a unified and expanded storage capacitor is formed, then the potential level of the pixel electrode is maintained more effectively and image homogeneity is improved, but the occupied area is increased, reducing the aperture ratio
Solution Approach 1:
The patent achieves expanded storage capacitance by stacking capacitors vertically across multiple insulation layers rather than expanding them horizontally. This vertical arrangement provides sufficient total capacitance to maintain pixel electrode potential stability and improve image homogeneity, while the compact horizontal footprint preserves a high aperture ratio.
Data Source
AI summary
Disclosed are a method for manufacturing a TFT substrate having storage capacitors and the TFT substrate. The method includes: (1) forming a gate terminal and a first metal electrode; (2) forming a gate insulation layer and a gate insulation layer through-hole; (3) forming an oxide semiconductor layer; (4) subjecting a portion of the oxide semiconductor layer to N-type heavy doping to form a first conductor electrode thereby constituting a first storage capacitor; (5) forming an etch stop layer and a first etch stop layer through-hole; (6) forming source/drain terminals and a second metal electrode, thereby constituting a second storage capacitor connected in parallel to the first capacitor; (7) forming a protection layer, a protection layer through-hole, and a second etch stop layer through-hole; and (8) forming a pixel electrode and a second conductor electrode, thereby constituting a third storage capacitor connected in parallel to the second capacitor.