TFT Substrate Triple-Layer Conductive Structure Etching
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Solution Overview
Problem
Current flat panel displays require high-performance thin film transistors (TFTs) to enhance color accuracy and response time, but existing TFT technologies have limitations in achieving optimal performance.
Innovation Solution
A TFT substrate design featuring a triple-layer conductive structure for data lines, source, and drain electrodes, with specific etching rates for each layer to form a groove that decreases in size, combined with a passivation layer and pixel electrodes, optimized for improved signal transmission and display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a triple-layer conductive structure is used for data lines, source, and drain electrodes, then signal transmission and display performance are enhanced, but manufacturing complexity increases
Solution Approach 1:
The conductive layer is divided into three distinct layers (first, second, and third layers) with different materials and functions. The first layer provides basic conductivity, the second layer enhances signal transmission, and the third layer provides protective and conductive properties. This segmentation allows each layer to be optimized independently for its specific function, resolving the contradiction between enhanced performance and structural complexity.
Solution Approach 2:
The patent employs composite material structure by combining different conductive materials across three layers. Each layer uses materials selected for specific properties (e.g., transparency, conductivity, etch resistance), creating a composite structure that achieves superior overall performance compared to single-material designs, while the systematic layering manages the complexity through functional differentiation.
2Manufacturing precision
If specific etching rates are applied to form a groove that decreases in size, then structural integrity and signal transmission are improved, but manufacturing precision requirements increase
Solution Approach 1:
Different etching rates are applied to different layers based on their local requirements. The first layer uses a first etching rate, the second layer uses a second etching rate, and the third layer uses a third etching rate. This local quality approach allows each layer to be etched with the precise rate needed for its specific function, achieving high manufacturing precision while managing the overall ease of manufacture through systematic differentiation.
Solution Approach 2:
The patent changes the etching rate parameter across different layers to achieve the desired groove profile. By systematically varying the etching rate parameter from one layer to the next, the patent creates a controlled gradient structure that improves structural integrity and signal transmission while making the etching process more manageable through parameter optimization.
3Reliability
If a passivation layer is added to cover electrodes and semiconductor layer, then device protection is improved, but device complexity increases
Solution Approach 1:
The passivation layer serves multiple functions simultaneously: it provides protective coverage for the underlying electrodes and semiconductor layer, establishes proper electrical insulation, defines precise boundaries for subsequent processing steps, and maintains structural integrity. This multi-functionality resolves the contradiction by achieving enhanced device protection without proportionally increasing complexity, as the single passivation layer performs multiple critical roles.
Data Source
AI summary
A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.


