TFT Substrate Via Formation Using Planarization Mask
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Solution Overview
Problem
The existing manufacturing methods for TFT substrates in liquid crystal display panels face issues with residues of the first transparent conductive film accumulating in vias, leading to incomplete development and affecting the quality of the TFT substrate.
Innovation Solution
A method that involves forming a first via and a second via in the planarization layer and first passivation layer to expose a portion of the drain terminal, using a photolithographic process and dry etching with the planarization layer as a self-aligning mask to prevent residues of the first transparent conductive film, and connecting the second pixel electrode through these vias to the drain terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photoresist layer is coated and exposed to form vias, then the via structure is created, but photoresist residues accumulate in the vias leading to incomplete development
Solution Approach 1:
The planarization layer is formed and patterned before the first transparent conductive film is deposited. This preliminary structuring creates a self-aligning mask that guides via formation and prevents photoresist accumulation by establishing proper via depth and geometry before the conductive film is in place.
Solution Approach 2:
The planarization layer serves as an intermediary mask layer between the photoresist and the first transparent conductive film. This intermediary structure controls the etching process and prevents photoresist residues from contaminating the via regions by providing a sacrificial masking layer.
2Productivity
If first transparent conductive film is deposited before via formation, then the pixel electrode can be formed, but residues of the conductive film remain in the vias affecting quality
Solution Approach 1:
The manufacturing process is segmented into distinct stages: first forming the planarization layer with via openings, then depositing the transparent conductive film only in regions that will become the pixel electrode (not in via regions), and finally forming the second pixel electrode. This segmentation prevents conductive film residues in vias while maintaining manufacturing efficiency.
Solution Approach 2:
The planarization layer is preliminarily formed and patterned to define via locations before the transparent conductive film deposition. This preliminary action ensures that subsequent etching steps create clean vias without conducting film residues, while still allowing efficient continuous processing.
3Device complexity
If conventional via formation method is used, then vias are created to connect electrodes, but misalignment occurs reducing aperture ratio
Solution Approach 1:
The planarization layer serves as a self-aligning mask that automatically aligns the vias with the drain terminal and subsequent electrode structures. This self-service alignment mechanism eliminates the need for complex external alignment procedures and ensures precise via positioning, maximizing the aperture ratio.
Solution Approach 2:
The planarization layer combines multiple functions: it provides surface planarity, serves as a self-aligning mask for via formation, and acts as a structural support layer. This merging of functions simplifies the overall device structure while ensuring precise via alignment and high aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents residues of the first transparent conductive film in the vias, enhancing product yield, reducing production costs, and improving the aperture ratio by minimizing misalignment, thus increasing the competitiveness of the TFT substrates.
Implementation Method 1
a photolithographic process is applied to the planarization layer for exposure to form a first via
Implementation Method 2
with the planarization layer serving as a self-aligning mask, dry etching is applied to the first passivation layer for etching to form a second via
Data Source
AI summary
The present invention provides a manufacturing method of a TFT substrate structure, which includes sequentially forming a first passivation layer, a planarization layer, and a first transparent conductive film and then first subjecting the first transparent conductive film to patterning to form a first pixel electrode and thereafter, a photolithographic process is applied to the planarization layer for exposure and thus forming a first via located above and corresponding to a drain terminal, followed by using the planarization layer as a self-aligning mask to apply dry etching to the first passivation layer for etching to form a second via that corresponds to the first via, whereby residues of the first transparent conductive film in the first and second vias can be effectively prevented and product yield is enhanced. Further, on mask can be saved to prevent reduction of aperture ratio caused by misalignment thereby improving the production efficiency, reducing production cost, and increasing cost-related competition power of products.