TFT Substrate Wiring Layout Flexibility via Dummy Gate Lines
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Solution Overview
Problem
The existing thin film transistor (TFT) substrate designs face challenges in maintaining flexibility of wiring layout due to the concentration of gate and source terminals on one side, leading to restricted flexibility in arranging drivers and wirings, especially when gate and source drivers are directly mounted on the frame region using the COG method.
Innovation Solution
The TFT substrate incorporates a design with gate signal lines, gate lead-out lines, and dummy gate lead-out lines that intersect, along with a common potential applied to dummy gate lead-out lines, and a shield electrode, allowing for a more flexible layout by distributing the wiring patterns and applying a common potential through common bus wiring and connection wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate terminal and source terminal are provided in the same side of the frame region, then the frame width can be narrowed, but the flexibility of wiring layout is reduced
Solution Approach 1:
The gate terminal is divided into multiple gate terminal electrodes (first gate terminal electrode and second gate terminal electrode) that are separated and positioned at different locations. This segmentation allows the wiring layout to maintain flexibility while achieving a narrower frame width, as the divided terminals can be strategically placed to optimize both space and connectivity.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking gate terminal electrodes at different positions (first and second gate terminal electrodes at different vertical locations). This dimensional approach allows multiple terminals to be accommodated within a compact horizontal space, thereby narrowing the frame width while preserving wiring layout flexibility through vertical arrangement.
2Quantity of substance
If gate lead-out lines are concentrated in one region, then the wiring density increases, but the loading effect increases and flexibility decreases
Solution Approach 1:
Different regions of the substrate are assigned different functions: the first region contains the first gate terminal electrode and associated lead-out lines, while the second region contains the second gate terminal electrode and its lead-out lines. This local differentiation allows wiring density to be optimized in each region independently, preventing excessive concentration in a single area and maintaining overall wiring flexibility.
Solution Approach 2:
The gate lead-out lines are segmented into multiple groups corresponding to different gate terminal electrodes. Instead of concentrating all lead-out lines in one location, they are distributed across multiple regions, which reduces the loading effect in any single region and preserves flexibility in the wiring layout.
Data Source
AI summary
A thin film transistor substrate includes: a plurality of gate signal lines extending in a first direction; a plurality of gate lead-out lines and a plurality of dummy gate lead-out lines extending in a second direction; a plurality of common lines extending in at least one of the first direction and the second direction in the pixel region; and a common electrode provided opposite to a pixel electrode and electrically connected to the plurality of common lines. The plurality of gate lead-out lines are connected to the gate signal lines at least at one point of a plurality of intersections between the plurality of gate signal lines and the plurality of gate lead-out lines, and the common potential is applied to the plurality of dummy gate lead-out lines.