Tapered Glue Layer Structure in TFT Electrodes for Lower Contact Resistance
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Solution Overview
Problem
Existing semiconductor devices, particularly thin film transistors, face challenges in reducing contact resistance (Rc) delay, which affects their performance.
Innovation Solution
The formation of a glue layer with varying growth rates on different materials, specifically on the sidewalls of source and drain electrodes, to improve adhesion without increasing resistance, using materials like WCN and WN, and forming a tapered end portion to ensure minimal contact at the bottom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a uniform thickness glue layer is formed on source and drain electrodes, then adhesion is improved, but contact resistance delay increases due to excessive glue material at the bottom
Solution Approach 1:
The glue layer thickness is made non-uniform with different thicknesses at different locations: thicker at sidewalls for adhesion, and thinner/minimal at bottom for reduced contact resistance. This local variation in thickness optimizes both adhesion strength and electrical contact properties.
Solution Approach 2:
The invention transitions from a two-dimensional uniform thickness approach to a three-dimensional variable thickness profile, creating a tapered shape that thickness varies in the vertical dimension while maintaining optimal contact at the bottom interface.
2Strength
If glue layer thickness is increased to improve adhesion, then adhesion strength improves, but contact resistance increases due to thicker glue at the bottom interface
Solution Approach 1:
Different regions of the glue layer serve different functions: the sidewall region has greater thickness for adhesion strength, while the bottom region has minimal thickness to reduce contact resistance, achieving both goals simultaneously through spatially differentiated properties.
Solution Approach 2:
The glue layer exhibits asymmetric thickness distribution rather than uniform symmetry, with the thickness profile being greater at the sidewalls and tapering to minimal thickness at the bottom, optimizing both mechanical and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance delay, enhancing the performance of the semiconductor devices by improving the adhesion of source and drain electrodes.
Implementation Method 1
a glue layer is formed in each the first and second openings, wherein a growth rate of the glue layer formed on the dielectric layer is different from a growth rate of the glue layer formed on the channel layer
Data Source
AI summary
A semiconductor device includes a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed over the substrate. The gate dielectric layer is disposed over the gate electrode. The channel layer is disposed over the gate dielectric layer. The source electrode and the drain electrode are disposed over the channel layer and beside the gate electrode. In some embodiments, each of the source electrode and the drain electrode includes a glue layer and a metal pattern, and a thickness of the glue layer adjacent to a sidewall of the metal pattern is greater than a thickness of the glue layer adjacent to a bottom of the metal pattern.