TFT Test Region and Electroluminescent Layer Evaluation in Display Panels
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Solution Overview
Problem
Conventional manufacturing technologies for liquid crystal display panels with low temperature polysilicon thin film transistors lack comprehensive evaluation of short-range uniformity and electrical characteristics of the electroluminescent layer and thin film transistors.
Innovation Solution
A display panel design with a peripheral area containing an electroluminescent layer test region and a TFT test region, connected by lead-out lines, allowing for the evaluation of the electroluminescent layer's display effect and the electrical characteristics, including short-range uniformity, of thin film transistors through specific voltage applications and probe measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional manufacturing technology is used for liquid crystal display panels with low temperature polysilicon thin film transistors, then the manufacturing process is simple, but the short range uniformity of the thin film transistor is relatively less tested and the display effect of the electroluminescent layer and the electrical characteristic of the thin film transistor cannot be evaluated comprehensively
Solution Approach 1:
The peripheral area is segmented into distinct functional regions: an electroluminescent layer test region for evaluating display effect, and a TFT test region for evaluating electrical characteristics including short range uniformity. This segmentation allows comprehensive testing while maintaining clear functional separation and manageable complexity.
Solution Approach 2:
The test structure serves multiple functions: it evaluates both the display effect of the electroluminescent layer and the electrical characteristics of thin film transistors simultaneously. The lead-out lines enable the TFT test region to measure electrical properties while the electroluminescent layer test region assesses optical performance, providing universal evaluation capability.
2Reliability
If the electroluminescent layer test region and TFT test region are added to the peripheral area, then comprehensive testing of display effect and electrical characteristics is enabled, but the device structure becomes more complex
Solution Approach 1:
Different regions of the peripheral area are designed with locally optimized structures: the electroluminescent layer test region contains thin film transistors with electroluminescent layers for display effect evaluation, while the TFT test region contains thin film transistors without electroluminescent layers for electrical characteristic evaluation. This local quality differentiation enables specialized testing in each region while maintaining overall structural coherence.
Solution Approach 2:
Lead-out lines serve as intermediaries connecting the source-drain metal layers of thin film transistors in the electroluminescent layer test region to corresponding thin film transistors in the TFT test region. These intermediary connections enable electrical characteristic measurements to be performed on TFTs while allowing the electroluminescent layer test region to maintain its display effect evaluation functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables comprehensive testing of the electroluminescent layer's display effect and thin film transistor characteristics, ensuring accurate evaluation and reflection of electrical properties in the display area.
Implementation Method 1
an electroluminescent layer test region comprising a plurality of thin film transistors having electroluminescent layers
Data Source
AI summary
A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.