Thin Film Transistor Array Substrate Test Terminal Design
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Solution Overview
Problem
Conventional liquid crystal display devices face challenges in accurately applying signals during the vision auto probe (VAP) test due to the narrow widths and small sizes of gate and data pads, leading to difficulties in probe alignment and contact, which can result in incomplete defect detection.
Innovation Solution
The introduction of gate and data test terminal units adjacent to the pad units allows probes to contact test terminals instead of the pad units directly, providing a larger contact margin and enabling accurate signal application, with the option to have two test terminal units on opposite sides to minimize signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If probes are aligned with gate pads and data pads directly, then test signal application is attempted, but misalignment occurs due to narrow widths and small sizes of pads
Solution Approach 1:
The patent introduces test terminal units as intermediary elements between the probes and the pad units. These test terminal units have larger sizes than the pad units, making them easier for probes to contact accurately. The test terminal units are electrically connected to the pad units through connection patterns, allowing test signals to be transmitted from the probes through the test terminal units to the pad units without requiring direct probe contact with the small pad units.
2Measurement precision
If test terminal units are provided adjacent to pad units, then probe contact accuracy is improved, but signal delay increases due to additional connection paths
Solution Approach 1:
The patent applies local quality by providing test terminal units selectively adjacent to specific pad units that require testing. The test terminal units are configured with appropriate sizes and shapes tailored to the specific testing requirements of adjacent pad units. The connection patterns are designed to establish electrical connections with minimal resistance and inductance, optimizing the local electrical characteristics to minimize signal delay while maintaining improved probe contact accuracy.
Data Source
AI summary
A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of gate pads extended from the gate lines, and a plurality of data pad units that groups a plurality of data pads extended from the data lines. The thin film transistor array substrate further includes a plurality of gate test terminals connected to the gate pad units and beside at least one side of the respective gate pad units, and a plurality of data test terminals connected to the data pad units and located beside at least one side of the respective data pad units.