Thin-Film Transistor Layout for Threshold Voltage Stability

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Solution Overview

Problem

Thin film transistors, particularly those with large channel widths, face challenges in controlling conductorization permeation depth and preventing threshold voltage shifts, which affect their reliability and driving stability.

Innovation Solution

The thin film transistor design includes a patterned active layer with specific conductorization control areas and diffusion areas, where the active layer is partially conductorized only in certain regions, controlling conductorization permeation depth and maintaining a stable threshold voltage by limiting conductorization to specific areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the channel width of the active layer is increased to improve current driving capacity, then the current driving capacity is improved, but the conductorization permeation depth becomes difficult to control and threshold voltage shifts in negative direction

Engineering Contradiction:
Improvecurrent driving capacityVSAvoidthreshold voltage stability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies local quality by creating different regions within the active layer with distinct properties: conductorization control areas where conductorization is permitted and diffusion barrier areas where it is prevented. This allows the channel width to be large for high current capacity while maintaining threshold voltage stability through localized control of conductorization in specific regions adjacent to the channel area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The active layer is segmented into functionally distinct regions: channel area, source area, drain area, conductorization control areas, and diffusion barrier areas. This segmentation enables independent optimization of each region's properties, allowing large channel width for high current while using diffusion barrier areas to prevent unwanted conductorization and maintain threshold voltage stability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If selective conductorization is applied to control conductorization area and permeation depth, then threshold voltage stability is improved, but device complexity increases due to additional process steps

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidprocess step complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-defining diffusion barrier areas within the active layer before conductorization processing. These barrier areas are strategically positioned to prevent conductorization permeation into the channel area, thereby proactively controlling threshold voltage stability and preventing negative shifts before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The diffusion barrier areas act as intermediary regions between the channel area and the source/drain areas. These intermediary zones prevent direct interaction between conductorized source/drain regions and the channel, thereby mediating the conductorization process and maintaining threshold voltage stability without requiring complex real-time control mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4383347A1Thin film transistor and display apparatus comprising the same
Publication Date: 2024.06.12 LG DISPLAY CO LTD
  • EP4383347A1 patent drawingFigure 1~2A
  • EP4383347A1 patent drawingFigure 2B~3
  • EP4383347A1 patent drawingFigure 4A~4B

AI summary

A thin film transistor (100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300) comprises an active layer (130); and a gate electrode (150) spaced apart from the active layer (130) to at least partially overlap the active layer (130) in a plan view. The active layer (130) includes a channel area (130a) that is overlapped by the gate electrode (150) in the plan view; a source area (130b) connected to one side of the channel area (130a) without being overlapped by the gate electrode (150) in the plan view; and a drain area (130c) connected to the other side of the channel area (130a) without being overlapped by the gate electrode (150) in the plan view. The source area (130b) and the drain area (130c) are spaced apart from each other with the channel area (130a) interposed therebetween. The active layer (130) includes a first source conductorization control area (135a) and a first drain conductorization control area (136a), which are spaced apart from each other. The first source conductorization control area (135a) corresponds to at least a portion of the channel area (130a) in the plan view, and the first drain conductorization control area (136a) corresponds to at least a portion of the channel area (130a) in the plan view.