TFT Array Substrate Trace Relocation for High Screen Ratio
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Solution Overview
Problem
The screen ratio of display panels cannot be further improved due to the significant area occupied by connection traces in non-display regions, which limits the achievement of 'full screen' designs in mobile devices.
Innovation Solution
A TFT array substrate design where gate and source signal lines are arranged in specific layers with trace holes to enable electrical connections between layers, allowing for the repositioning of gate and source traces from non-display regions into display regions, thereby reducing the non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection traces are disposed in non-display regions, then electrical connections between control circuits and TFT layers are achieved, but the area occupied by connection traces increases, reducing screen ratio
Solution Approach 1:
The patent transitions from a single-layer trace layout to a multi-layer wiring structure. Connection traces are distributed across multiple layers (first planar layer, second planar layer, and intermediate layers) with vertical connections through trace holes. This dimensional expansion allows traces to be stacked vertically rather than spreading horizontally, reducing the footprint in non-display regions while maintaining electrical connectivity.
Solution Approach 2:
The patent implements a nested wiring architecture where traces in different layers are interconnected through trace holes. The first gate traces and second gate traces are nested vertically, connected via first gate trace holes. Similarly, source traces are nested across layers connected through source trace holes. This nesting allows compact arrangement of connection paths in the vertical dimension, minimizing horizontal space occupation.
2Area of stationary object
If screen ratio is increased by reducing non-display region, then display area proportion improves, but trace routing complexity increases
Solution Approach 1:
The patent segments the connection traces into multiple sections distributed across different layers. Gate traces are divided into first gate traces (in first planar layer) and second gate traces (in second planar layer), connected through first gate trace holes. Source traces are similarly segmented into first source traces and second source traces connected through source trace holes. This segmentation allows each layer to handle specific routing tasks, simplifying the overall routing complexity while achieving compact layout.
Solution Approach 2:
The patent introduces trace holes as intermediary elements to connect traces between layers. First gate trace holes serve as intermediaries connecting first gate traces and second gate traces. Source trace holes similarly mediate connections between source trace sections. These intermediary vertical connections enable complex multi-layer routing while maintaining manageable complexity through standardized connection interfaces.
Data Source
AI summary
A thin film transistor (TFT) array substrate and a display panel are provided in the present application. The TFT array substrate includes a plurality of gate signal lines, a plurality of source signal lines, a plurality of gate traces, the gate traces including a plurality of first gate traces, a plurality of second gate traces, a plurality of first gate trace holes, and a plurality of second gate trace holes; a plurality of source traces, the source traces including a plurality of first source traces, a plurality of second source traces, a plurality of first source trace holes, and a plurality of second source trace holes connecting the source signal lines and the first source traces.