Display Device Thin Film Transistor Vertical Stacking
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Solution Overview
Problem
The existing organic EL display devices face limitations in pixel fineness due to the arrangement and structure of circuit components, which become constrained when pixel size is reduced.
Innovation Solution
The display device incorporates a thin film transistor with a semiconductor layer, a channel region, a gate electrode, and electrodes that include an overlapped region with a conductive layer, allowing for improved circuit component arrangement and increased pixel fineness by enhancing capacitance and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel size is reduced to improve fineness, then display resolution is improved, but the arrangement and structure of circuit components become limited
Solution Approach 1:
The patent utilizes vertical stacking to arrange circuit components in multiple layers (first and second circuit components at different heights), transforming a two-dimensional layout problem into a three-dimensional structure. This allows more components to be integrated within a smaller pixel area by exploiting the vertical dimension, thereby maintaining pixel fineness while accommodating necessary circuit elements.
Solution Approach 2:
The patent implements nested arrangement where circuit components are positioned within overlapping regions. Specifically, the first circuit component is arranged in a region that overlaps with the second circuit component when viewed from above, allowing components to be nested within each other's projection area. This nesting strategy maximizes space utilization and enables finer pixel design.
2Manufacturing precision
If circuit components are arranged to improve pixel fineness, then pixel size is reduced, but capacitance may be insufficient
Solution Approach 1:
The patent forms capacitance components by stacking conductive layers vertically, creating overlapping regions in the vertical dimension. The first and second capacitance components are formed by overlapping conductive layers at different heights, effectively utilizing vertical space to generate sufficient capacitance within a reduced pixel area.
Solution Approach 2:
The patent combines multiple functions into overlapping regions where conductive layers serve both as interconnect structures and as capacitance-forming elements. The same overlapping conductive layers that provide electrical connections also function as capacitance components, merging routing and storage functions to maximize space efficiency.
3Ease of manufacture
If conventional wiring structures are used, then manufacturing is simple, but parasitic capacitance between scanning lines and auxiliary wiring increases
Solution Approach 1:
The patent separates scanning lines and auxiliary wiring into different vertical layers, utilizing the vertical dimension to reduce horizontal overlap. By arranging these conductors at different heights, the parasitic capacitance between them is minimized while maintaining a relatively simple manufacturing process that extends conventional planar wiring into three-dimensional space.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between conductive layers that need to be electrically isolated. These insulating layers act as mediators that prevent direct electrical interaction between scanning lines and auxiliary wiring, thereby reducing parasitic capacitance while allowing the wiring structures to be formed in close proximity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables more efficient current control and light emission, improving pixel fineness and display quality by increasing auxiliary capacitance and storage capacitance while minimizing parasitic capacitance.
Implementation Method 1
a gate electrode which overlaps the channel region in plan view
Implementation Method 2
the conductive layer includes an overlapped region which overlaps with the channel region in plan view, and the first electrode extends so as to cover the gate electrode at the overlapped region
Data Source
AI summary
A display device includes a display region comprising a plurality of pixels, each pixel of the plurality of pixels comprises a light emitting element which includes a pixel electrode, a conductive layer below the pixel electrode and configured to receive a specified electric voltage, and a thin film transistor below the pixel electrode and the conductive layer, wherein the thin film transistor comprises a semiconductor layer which includes a channel region, a gate electrode which is overlapping the channel region, a first electrode electrically connected to the semiconductor layer and the pixel electrode, and a second electrode electrically connectable to a power supply line, wherein the conductive layer includes an overlapped region which overlaps with the channel region, and the first electrode extends so as to cover the gate electrode at the overlapped region.