Thin Film Transistor Substrate Via Deposition and Etch Stopper Patterning
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Solution Overview
Problem
The existing manufacture methods for thin film transistor substrates, particularly those using an etch stopper layer structure, require additional photolithographic processes, increasing production costs and reducing yield due to the need for extra processing steps.
Innovation Solution
Implementing the via deposing process for both the gate isolation layer and the etching stopper layer in a single photolithographic process, allowing for the elimination of one extra photolithographic step and enhancing the aperture ratio by forming an open at the transparent conducting layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching stopper layer is formed to protect the oxide semiconducting layer, then the stability of the thin film transistor is improved, but an additional photolithographic process is required which increases manufacturing cost and reduces yield
Solution Approach 1:
The patent combines the via deposing process and etching stopper layer patterning into a single photolithographic process. The photoresist layer is patterned to define both the via openings in the gate isolation layer and the etching stopper layer pattern simultaneously. This merging of two separate photolithographic steps into one reduces process complexity and manufacturing cost while maintaining the protective function of the etching stopper layer.
2Reliability
If an etching stopper layer is formed to prevent damages in following processes, then the stability of the oxide semiconducting thin film transistor is promoted, but the manufacture cost will be enormously increased and the production yield is descending
Solution Approach 1:
The patent merges the via deposing process and etching stopper layer formation into a single photolithographic step. By using one photoresist layer to define both the via openings and the etching stopper pattern, the number of process steps is reduced, which directly improves production yield and reduces manufacturing cost while still providing the necessary protection to the oxide semiconducting layer.
3Reliability
If an etching stopper layer is formed to protect the oxide semiconducting layer, then the stability is promoted, but one photolithographic process comprises manufacture processes of thin film, photo, etching, stripping which increases cost
Solution Approach 1:
The patent combines two separate photolithographic processes (via deposing and etching stopper layer formation) into a single process step. The photoresist layer is patterned to simultaneously define both features, eliminating the need for separate thin film deposition, photo patterning, etching, and stripping steps for each feature. This merging significantly reduces manufacturing cost and process complexity while maintaining the protective function of the etching stopper layer.
Data Source
AI summary
The present invention provides a manufacture method of a thin film transistor substrate. In the same photolithographic process, the via deposing process is implemented to the gate isolation layer and the etching stopper layer is patterned. That is, the photolithographic process is not implemented but the oxide semiconducting pattern is formed directly after the gate isolation layer is formed. After the etching stopper layer is formed, the gate isolation layer and the etching stopper layer are patterned in the same photolithographic process. Comparing with the manufacture method of prior art, one photolithographic process can be eliminated. Meanwhile, the aperture ratio is raised by forming an open at the transparent conducting layer.