Thin-Film Transistor Via-Gate Structure for Stable Gate Control
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Solution Overview
Problem
Conventional thin-film transistor (TFT) fabrication processes face challenges in scaling to sub-10 nm dimensions due to variability and limitations in sub threshold swing, leading to performance issues and difficulties in integrating advanced semiconductor devices.
Innovation Solution
The integration of a combined via and gate electrode structure in TFTs, allowing for increased gate control and stability through a unified processing step, which enhances channel length and reduces interface breaks, facilitating fabrication of non-planar BEOL transistors with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional separate via and gate electrode fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision and device performance deteriorate at sub-10 nm dimensions
Solution Approach 1:
The patent combines the via and gate electrode into a single unified structure formed by one continuous deposition process. This merging eliminates the need for separate fabrication steps for via formation and gate electrode deposition, thereby improving manufacturing precision at sub-10 nm dimensions while reducing overall process complexity through integration.
Solution Approach 2:
The unified conductive structure serves multiple functions simultaneously: it acts as both the via (connecting lower interconnect) and the gate electrode (controlling the channel). This multi-functionality approach improves device performance by ensuring precise alignment and intimate contact between structures that would otherwise require separate fabrication processes.
2Reliability
If separate via and gate electrode structures are used, then process flexibility is maintained, but interface breaks and reduced stability occur
Solution Approach 1:
By merging the via and gate electrode into a single conductive structure deposited in one step, the patent eliminates the interface between separate via and gate electrode materials. This continuous structure prevents interface breaks and ensures stable electrical contact, directly improving reliability while the unified process maintains sufficient adaptability for various device configurations.
3Length of moving object
If conventional fabrication processes are used, then existing infrastructure compatibility is maintained, but channel length control and gate control deteriorate
Solution Approach 1:
The patent transitions from planar separate structures to a three-dimensional unified conductive structure that extends vertically and horizontally. This dimensional change allows precise control of channel length through the continuous structure's geometry while maintaining fabrication simplicity through single-step deposition, overcoming limitations of conventional two-dimensional separate structure fabrication.
Data Source
AI summary
Thin film transistors are described. An integrated circuit structure includes a first dielectric layer having a conductive interconnect therein. A second dielectric layer is above the first dielectric layer. A conductive structure is in the second dielectric layer and in contact with the conductive interconnect. The conductive structure includes a lower conductive via portion continuous with an upper gate electrode portion that extends above and onto an uppermost surface of the second dielectric layer. A gate dielectric layer is on the upper gate electrode portion of the conductive structure. A channel material layer is on the gate dielectric layer. Source or drain contacts are on the channel material layer.