Thin Film Transistor Via Hole Design for Narrow Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Metal oxide thin film transistors (TFTs) face challenges in stability and performance due to large channel lengths, which restrict their mobility and display effect, compared to amorphous silicon TFTs, and conventional fabrication processes require multiple masks and complex patterning steps.
Innovation Solution
A thin film transistor design with source and drain electrodes connected through via holes in both the etch stop layer and active layer, utilizing an electrically conductive layer with nanoparticles for improved conductivity, allowing for a single patterning process to form these connections, thereby shortening the channel length and enhancing mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal oxide TFT fabrication processes are used with multiple masks and complex patterning steps, then the stability of array substrate is improved, but the device complexity and manufacturing time are increased
Solution Approach 1:
The patent combines the formation of source and drain electrodes with the formation of electrically conductive layers into a single patterning process. The source electrode, drain electrode, and electrically conductive layers are formed simultaneously using one mask and one patterning step, eliminating the need for multiple separate patterning operations while maintaining structural integrity and electrical connectivity.
Solution Approach 2:
The single patterning process serves multiple functions: it defines the source electrode pattern, defines the drain electrode pattern, and forms the electrically conductive layers that connect to both source and drain regions. This multi-functional approach replaces what would traditionally require multiple specialized patterning steps.
2Reliability
If conventional metal oxide TFT fabrication processes are used with multiple masks, then the connection stability between source/drain electrodes and active layer is improved, but the manufacturing time and productivity are reduced
Solution Approach 1:
The patent merges multiple fabrication operations into a single patterning process. The source electrode, drain electrode, and electrically conductive layers are formed in one step using a single mask, reducing the total number of patterning cycles from multiple to one, thereby significantly improving manufacturing throughput while ensuring stable electrical connections.
Solution Approach 2:
The electrically conductive layers are formed preliminarily within the same patterning process that creates the source and drain electrodes. This preliminary formation of conductive pathways ensures that connections are established early in the process, maintaining stability while reducing overall manufacturing time.
3Reliability
If large channel length is used in metal oxide TFTs, then the stability is improved, but the mobility and charging rate are reduced
Solution Approach 1:
The patent introduces a vertical dimension by forming via holes through the gate insulation layer to create direct electrical connections between the electrically conductive layers and the source/drain regions. This three-dimensional connection approach allows for shorter effective channel lengths while maintaining stable connections, thereby improving charging rate without sacrificing reliability.
Solution Approach 2:
The electrically conductive layers act as intermediaries that bridge the source/drain electrodes and the active layer through via holes. These intermediary conductive paths enable efficient charge transport with shorter effective channel lengths, improving mobility and charging rate while the via hole structure maintains connection stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design results in a narrow channel TFT with increased charging rate and improved display effect, simplifying the fabrication process by reducing the number of masks required and enhancing the transistor's performance.
Implementation Method 1
utilizing an electrically conductive layer with nanoparticles for improved conductivity
Data Source
Figure 1~2
Figure 3~6
Figure 7~9
AI summary
A thin film transistor and a preparation method therefor, an array substrate and a display apparatus. The thin film transistor comprises an active layer (4), an etched barrier layer (5) disposed on the active layer (4), and a source and drain (6) disposed on the etched barrier layer (5). The source and drain (6) are disposed on a same layer in a spaced manner. First via holes (7) are formed in the etched barrier layer (5), second via holes (8) are formed in positions in the active layer (4) corresponding to the first via holes (7). The source and drain (6) are connected to the active layer (4) through the first via holes (7) formed in the etched barrier layer (5) and the second via holes (8) formed in the active layer (4). Because two second via holes are formed in the active layer, a design value L1 of the channel region length of the active layer is shortened and a metal oxide semiconductor array substrate with a narrow channel is formed and the charge rate is high, which helps to improve the display effect.