3D Memory Thin-Film Transistors With Via-Based Deck Selection
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Solution Overview
Problem
The challenge in increasing memory cell density in three-dimensional memory devices while minimizing the size of complementary metal oxide semiconductor (CMOS) circuitry, which offsets the benefits of 3D integration, and the need for efficient fabrication techniques to construct thin film transistors (TFTs) that can select or inhibit memory decks without increasing substrate area.
Innovation Solution
The development of fabrication techniques that allow for the concurrent construction of multiple decks of memory cells and array electrodes using a pattern of vias, with thin film transistors (TFTs) integrated in array layers to select or inhibit memory decks, reducing the thermal budget and manufacturing costs, and enabling flexible process optimization to mitigate processing conditions such as thermal impacts and cross-contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased in three-dimensional memory devices, then storage capacity improves, but CMOS circuitry area expands offsetting the benefits of 3D integration
Solution Approach 1:
The patent implements thin film transistors with vertically oriented channels extending through multiple decks of memory cells in the vertical dimension. This allows the TFTs to control memory access in three-dimensional space without requiring additional lateral area, thereby increasing memory cell density while maintaining compact CMOS circuitry footprint.
Solution Approach 2:
The patent integrates TFTs within the array layers alongside memory cells, nesting the transistor structures within the same vertical stack. The TFT channels extend vertically through multiple memory cell decks, allowing the transistors to be embedded within the three-dimensional memory structure rather than occupying separate lateral space.
2Adaptability or versatility
If thin film transistors are integrated in array layers to select or inhibit memory decks, then memory deck selection capability improves, but fabrication complexity increases
Solution Approach 1:
The patent combines the fabrication processes for TFTs and memory cells into a unified sequence. The same deposition and etching steps that form memory cell structures also create TFT components, merging two fabrication workflows into one integrated process that reduces overall complexity despite the enhanced functionality.
Solution Approach 2:
The patent employs universal fabrication steps that simultaneously create both memory cell structures and TFT components. Materials and processes used for memory cell formation are also applied to TFT gate, channel, and contact formation, allowing a single fabrication sequence to deliver multiple functional elements.
3Ease of manufacture
If conventional fabrication techniques are used for TFTs and memory cells, then manufacturing process is simpler, but thermal impacts and cross-contamination increase
Solution Approach 1:
The patent segments the fabrication process into distinct modules with intermediate cleaning and protective steps. By dividing the concurrent TFT and memory cell fabrication into separable stages, the process can address thermal management and contamination control at each segment while maintaining overall manufacturing efficiency.
Data Source
AI summary
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.