Array Substrate Transfer Structure for TFT-LCD Peripheral Alignment
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Solution Overview
Problem
The periphery of TFT-LCD displays experiences rubbing alignment shadows and uneven liquid crystal diffusion due to peripheral wiring, leading to light leakage and yield reduction in display products.
Innovation Solution
An array substrate design with specific via holes and transfer structures that electrically connect gate and common signal lines to leads, reducing the influence of peripheral wiring on the display area and improving liquid crystal orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral wiring area is present in TFT-LCD, then electrical connection and signal transmission are enabled, but rubbing alignment shadows and uneven liquid crystal diffusion occur in the periphery of display area
Solution Approach 1:
The patent extracts the problematic peripheral wiring structure from the display area by introducing a shielding layer that isolates the wiring region. The shielding layer is positioned between the peripheral wiring and the liquid crystal molecules, effectively separating the electrical connection function from the liquid crystal orientation region, thereby preventing rubbing alignment shadows and uneven diffusion.
Solution Approach 2:
The shielding layer acts as an intermediary element between the peripheral wiring and the liquid crystal layer. This intermediate structure prevents direct interaction between the wiring and liquid crystal molecules, blocking the harmful effects of rubbing and electrical fields while maintaining the necessary electrical connections in the peripheral region.
2Reliability
If peripheral wiring area is present in TFT-LCD, then signal transmission is enabled, but light leakage and dark areas occur in the periphery of display area
Solution Approach 1:
The patent extracts the light shielding function from the display structure by adding a dedicated shielding layer in the peripheral wiring area. This layer selectively blocks light in the wiring region while maintaining light transmission in the active display area, thereby preventing light leakage and dark area defects without affecting signal transmission.
Solution Approach 2:
The shielding layer serves as an intermediary that mediates between the peripheral wiring and the light field. It selectively absorbs or blocks light in the peripheral region where wiring is present, preventing light leakage and display uniformity issues while allowing the wiring to continue its signal transmission function.
3Ease of manufacture
If conventional array substrate structure is used, then manufacturing process is simple, but yield of display products is reduced due to peripheral defects
Solution Approach 1:
The patent segments the array substrate into distinct functional regions: a display area with liquid crystal molecules and a peripheral wiring area with a shielding layer. This segmentation allows the shielding layer to be added specifically in the peripheral region where needed, without complicating the overall manufacturing process or affecting the simplicity of producing the main display area.
Solution Approach 2:
The shielding layer is formed in advance during the manufacturing process, before the liquid crystal assembly is completed. This preliminary action prevents peripheral defects from occurring in the first place, thereby improving product yield without requiring additional complex post-processing steps.
Data Source
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AI summary
An array substrate and a display device. The array substrate is provided with a display region (A) and a peripheral wiring region (B) arranged on at least one side of the display region (A). The display region (A) comprises a thin film transistor (12) and a common electrode (13) which are formed on a base substrate (11); and the peripheral wiring region (B) comprises a first lead (18), a gate signal line (19) and a common signal line (20) which are formed on the base substrate (11). The first lead (18) is arranged on the same layer as a gate (120) of the thin film transistor (12) and is electrically connected with the gate (120); the gate signal line (19) is located at the side of the first lead (18) away from the base substrate (11).