Top-Gate Self-Aligned ITZO TFT for Low Parasitic Capacitance
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Solution Overview
Problem
Traditional bottom-gate ITZO TFTs suffer from large parasitic capacitance and weak device scalability, and top-gate self-aligned TFTs with plasma-treated source and drain regions exhibit poor thermal stability and increased manufacturing costs due to additional doping process steps.
Innovation Solution
A top-gate self-aligned ITZO TFT with a silicon dioxide or silicon nitride buffer layer, an ITZO thin film comprising low-resistivity source and drain regions and a high-resistivity channel region, and a method involving chemical vapor deposition for gate and passivation layers, eliminating the need for ion doping and reducing parasitic capacitance and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plasma treatment is used to form highly conductive source and drain regions, then electrical conductivity is improved, but thermal stability deteriorates due to ion diffusion accelerated by thermal treatments
Solution Approach 1:
The patent extracts and eliminates the plasma treatment step from the manufacturing process. Instead of using plasma to create highly conductive source and drain regions, the invention uses a different approach that forms conductive regions without introducing dopant ions that would diffuse during thermal treatments, thereby resolving the thermal stability issue while maintaining electrical conductivity
Solution Approach 2:
The patent changes the method of forming conductive regions from plasma-based doping to an alternative formation mechanism. By altering the physical and chemical parameters of the source and drain region formation process, the invention achieves high conductivity without the harmful side effect of ion diffusion during subsequent thermal steps
2Reliability
If plasma treatment and ion doping are used to form highly conductive source and drain regions, then electrical conductivity is improved, but manufacturing cost increases due to additional process steps
Solution Approach 1:
The patent removes the plasma treatment and ion doping steps from the manufacturing process. By extracting these complex and costly process steps, the invention simplifies the manufacturing workflow while still achieving the desired highly conductive source and drain regions through an alternative method
Solution Approach 2:
The invention enables the source and drain regions to become self-conductive through the inherent properties of the ITZO thin film and the deposition process itself, rather than requiring external plasma treatment or ion doping steps. This self-service approach eliminates additional process steps and reduces manufacturing complexity
3Ease of manufacture
If bottom-gate structure is used, then manufacturing is simpler, but parasitic capacitance increases and device scalability weakens
Solution Approach 1:
The patent inverts the traditional bottom-gate structure to a top-gate configuration. By placing the gate electrode on top of the ITZO thin film rather than at the bottom, the invention reduces parasitic capacitance between the gate and source/drain regions while improving device scalability for high-resolution displays, without significantly complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves small parasitic capacitance, strong device scalability, and robust thermal stability while reducing manufacturing costs by forming low-resistivity source and drain regions without ion doping, enhancing the performance and stability of the TFTs.
Implementation Method 1
depositing a gate dielectric layer on the patterned ITZO thin film by using a first chemical vapor deposition method; depositing a passivation layer on the conductive thin film and the ITZO thin film by using a second chemical vapor deposition method
Data Source
AI summary
The TG-SA ITZO TFT comprises a substrate, a buffer layer, an ITZO thin film, a gate dielectric layer, a conductive thin film, a passivation layer, gate, source and drain contact electrodes. The transistor has a TG-SA structure, which can address the issues of larger parasitic capacitance and weaker device scalability in a traditional bottom-gate counterpart. When depositing the gate dielectric layer and the passivation layer, different gas sources and annealing conditions are used, such that the ITZO thin film region contacted with and covered by the gate dielectric layer shows a high-resistivity state, the ITZO thin film region contacted with and covered by the passivation layer shows a low-resistivity state, thereby forming a high-resistivity channel region and low-resistivity conductive source and drain regions, and addressing the thermal instability issue.