Thermal-Aware Interrupt Controller Routing for CPU Core Limits

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Solution Overview

Problem

Processor-based systems face challenges in managing thermal limits during interrupt handling, leading to potential thermal violations and reduced performance due to sudden increases in power consumption, especially in environments with higher ambient temperatures.

Innovation Solution

Implementing a thermal-aware interrupt controller that prioritizes interrupts based on CPU core temperatures and thermal limits, selectively routing them to eligible CPU cores that can handle the interrupts without exceeding thermal thresholds, thereby avoiding thermal mitigation and maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If interrupt handling is performed by any eligible CPU core without thermal awareness, then interrupt response time is improved, but thermal violations may occur causing performance degradation

Engineering Contradiction:
Improveinterrupt response timeVSAvoidCPU core temperature
Core Design Contradiction:
SpeedVSTemperature

Solution Approach 1:

The interrupt controller proactively checks the temperature status of eligible CPU cores before routing an interrupt, and selectively routes the interrupt only to cores that can handle it without exceeding thermal thresholds. This preliminary thermal awareness prevents thermal violations before they occur, maintaining both fast interrupt response and safe operating temperatures.

Inventive Principle:
Principle #10Preliminary action

2Temperature

If CPU core frequency is reduced to avoid thermal violations, then thermal limits are maintained, but system performance decreases

Engineering Contradiction:
ImproveCPU core temperatureVSAvoidsystem performance
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The system applies thermal-aware interrupt routing at the local level of individual CPU cores, allowing each core to be evaluated independently based on its current temperature status. This enables interrupts to be routed to specific cores that have thermal headroom, rather than globally reducing frequency of all cores, thus maintaining high performance while respecting thermal limits.

Inventive Principle:
Principle #3Local quality

3Productivity

If interrupts are routed without considering thermal status, then interrupt handling efficiency is improved, but sudden power consumption increases may cause thermal violations

Engineering Contradiction:
Improveinterrupt handling efficiencyVSAvoidthermal violations from interrupt handling
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The interrupt controller continuously monitors the temperature status of CPU cores and uses this feedback information to make intelligent routing decisions. By incorporating real-time thermal status into the interrupt routing logic, the system can direct interrupts to cores that have the capacity to handle them without causing thermal violations, thereby maintaining both efficiency and thermal safety.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250217181A1Thermal-aware interrupt routing in an interrupt controller in processor-based systems, and related methods
Publication Date: 2025.07.03 QUALCOMM INC
  • US20250217181A1 patent drawing
  • US20250217181A1 patent drawing
  • US20250217181A1 patent drawing

AI summary

Thermal-aware interrupting routing in an interrupt controller in processor-based systems, and related methods are disclosed. The processor-based system includes one or more interrupt controllers that are each configured to prioritize interrupts received from components in the processor-based system and direct each received interrupt to a CPU core(s) in its designated processor to perform an interrupt service routine (ISR) to process the interrupt. To avoid or reduce the likelihood of the interrupt controller directing an interrupt to a CPU core(s) and/or CPU core cluster(s) that may exceed its thermal limit by accepting and handling the interrupt, the interrupt controller is configured to be aware of temperatures of the CPU cores and/or the CPU core clusters in its designated processor. The interrupt controller is configured to selectively route received interrupts based on temperature of the CPU core(s) and/or their CPU core cluster(s) that were determined eligible to receive and handle the interrupt.