Thermal Head Substrate Clock Signal Routing for Noise Reduction
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Solution Overview
Problem
The existing thermal printer head substrates face challenges in miniaturization and cost reduction due to complex layouts and noise interference from clock signal lines, which increase the physical size and area of the thermal head.
Innovation Solution
The thermal head substrate design incorporates a configuration where part of the clock signal and logic power lines are disposed between the driver IC mounting regions, reducing the number of input signal wiring lines and minimizing noise effects by placing the logic power line adjacent to the clock signal line, thus reducing the area occupied by the input signal wiring pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the clock signal line and latch signal line are disposed on the mounting region of the driver IC, then the input signal wiring pattern can be simplified and the area can be reduced, but the high-frequency clock signal noise affects other portions especially output lines of head driving signals causing errors
Solution Approach 1:
The substrate is divided into distinct regions: a mounting region for the driver IC and a signal wiring region for signal transmission. This segmentation allows the clock signal line to be placed in the mounting region without interfering with output signal lines in the signal wiring region, thus maintaining signal reliability while utilizing the mounting region space effectively
Solution Approach 2:
The clock signal line is extracted from the signal wiring region and placed in the mounting region of the driver IC. This extraction removes the source of noise from the sensitive signal transmission area, preventing noise interference with output lines while still allowing the clock signal to reach the driver IC through the input signal wiring pattern
2Productivity
If four driver ICs are arranged to drive 512 heater elements, then each driver IC can control 128 heater elements, but 128×4 separate electrode patterns and multiple input signal wiring patterns increase the layout complexity and substrate area
Solution Approach 1:
The input signal wiring patterns for all four driver ICs are merged into a unified routing structure. The clock signal line and other input signals are routed through the mounting region to multiple driver ICs simultaneously, reducing the overall complexity of the wiring layout while maintaining the capability to drive all 512 heater elements through the four driver ICs
Solution Approach 2:
The mounting region of the driver IC serves multiple functions: it provides the physical mounting area for the driver IC package and simultaneously acts as a conduit for input signal wiring patterns including the clock signal line. This multi-functionality reduces the need for separate wiring regions and simplifies the overall substrate layout
Data Source
AI summary
A head substrate for mounting a driver IC that selectively drives a plurality of driving elements is provided. An input signal wiring pattern electrically connects external connection terminals with the pads in a first pad array and a second pad array. The input signal wiring pattern includes a clock signal line for supplying the clock signal to the driver IC and a logic power line for supplying the logic power to the driver IC. A part of the clock signal line and a part of the logic power line are disposed between the first pad array and the second pad array.