Thermal-Only Pads for Cryogenic IC Heat Sinking

Solution Overview

Problem

High power chips operating at cryogenic temperatures face challenges in thermal management due to poor thermal conductivity at low temperatures, especially when there are electrical contacts on both sides, as traditional thermal interface materials perform poorly and direct contact can cause electrical shorting or chip damage.

Innovation Solution

The use of thermal-only pads bump-bonded to a low CTE heat spreader, such as Au/Pt plated Molybdenum, which are then clamped or attached to a cryogenic platform, providing direct metal-to-metal heat transfer without electrical interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If traditional thermal interface materials (adhesives, gels, epoxies) are used to bond the chip to the heat sink, then the bonding process is simple, but the thermal conductivity at cryogenic temperatures is poor

Engineering Contradiction:
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent introduces an intermediary metal layer (such as tungsten, molybdenum, or copper) between the chip and the heat sink. This metal intermediary maintains good thermal conductivity at cryogenic temperatures while providing a mechanically robust bonding interface, replacing the traditional thermal interface materials that fail at low temperatures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs composite material structures combining different metals with complementary properties. The chip is bonded to a metal heat spreader (e.g., tungsten or molybdenum with low thermal expansion) which is then attached to the heat sink, creating a composite thermal management system that maintains structural integrity and thermal performance at cryogenic temperatures.

Inventive Principle:
Principle #40Composite materials

2Temperature

If the chip is clamped with great force to improve thermal contact, then thermal conductivity improves, but the chip may break due to stress

Engineering Contradiction:
Core Design Contradiction:
TemperatureVSStrength

Solution Approach 1:

The patent uses a compliant metal intermediary layer (such as gold, silver, or copper) between the chip and the rigid heat sink. This compliant layer acts as a stress buffer that distributes clamping forces evenly across the chip surface, preventing localized stress concentrations that could cause chip fracture while maintaining intimate thermal contact.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the mechanical parameters of the bonding interface by using materials with appropriate yield strengths and elastic moduli. The metal intermediary layer is selected to have mechanical properties that allow it to deform plastically under clamping stress, absorbing the mechanical energy and protecting the fragile chip from damage.

Inventive Principle:
Principle #35Parameter changes

3Temperature

If direct contact between chip and heat sink is used to maximize thermal transfer, then thermal conductivity is maximized, but electrical shorting or chip damage may occur

Engineering Contradiction:
Core Design Contradiction:
TemperatureVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a metal intermediary layer that serves dual functions: it provides excellent thermal conductivity for efficient heat transfer while simultaneously acting as an electrical isolation barrier. This intermediary layer prevents direct electrical contact between the chip electrodes and the heat sink, eliminating the risk of electrical shorting while maintaining thermal performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Temperature

If liquid helium is used for cooling to achieve effective heat sinking, then cooling performance is improved, but the system becomes complex and consumes large amounts of precious helium

Engineering Contradiction:
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent uses a metal intermediary heat spreader layer (such as tungsten, molybdenum, or copper) with high thermal conductivity that enables efficient heat transfer from the chip to the heat sink without requiring liquid helium. This intermediary structure creates a solid-state thermal management system that is simpler, more reliable, and eliminates dependence on cryogenic liquids.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances thermal management by avoiding the need for liquid helium and reducing the risk of chip damage, offering better thermal conductivity and electrical isolation, thus effectively managing heat sinking at cryogenic temperatures.

Implementation Method 1

providing direct metal-to-metal heat transfer without electrical interference

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

thermal-only pads bump-bonded to a low CTE heat spreader

Methodology Applied
Scientific EffectMetallurgical bonding: Welding

Data Source

PatentUS20230108475A1Thermal management techniques for high power integrated circuits operating in dry cryogenic environments
Publication Date: 2023.04.06
  • US20230108475A1 patent drawing
  • US20230108475A1 patent drawing
  • US20230108475A1 patent drawing

AI summary

Improved heat sinking of electronic and/or photonic integrated circuit chips is provided by including thermal-only contacts on unused parts of the chip. The resulting chip can be bonded to a cold plate with a process that ensures that only the thermal contacts of the chip touch the cold plate, thereby avoiding problems caused by the cold plate creating electrical shorts of the chip. For example, the thermal contacts can be higher features than any electrical features on that side of the chip. This approach is expected to be especially useful for applications requiring low temperature operation (e.g., operation at 100K or less, preferably operation at 10 K or less).