Thermal Oxidation Via Insulation for High-Density TSV Alignment

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Solution Overview

Problem

Existing through silicon via (TSV) formation methods result in poor-quality insulation due to low-temperature silicon oxide deposition, leading to degraded electric performance and reduced via integration density, as well as alignment issues when forming vias after electronic components are created.

Innovation Solution

The method involves forming openings in the substrate, thermally oxidizing the walls, filling with a sacrificial material, forming electronic components, etching the sacrificial material, and then filling with metal, allowing for high-quality thermal oxide insulation and closer via placement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If low-temperature CVD is used to deposit silicon oxide insulation layer, then the deposition temperature is kept below 200°C, but the insulation quality is poor and non-conformal

Engineering Contradiction:
Improvedeposition temperatureVSAvoidinsulation conformality
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The patent changes the deposition temperature parameter from low-temperature CVD (<200°C) to high-temperature thermal oxidation (>1000°C). This parameter change transforms the deposition process into a thermal oxidation process that produces high-quality conformal silicon oxide insulation layers, resolving the contradiction between temperature control and insulation quality.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If vias are formed after electronic components are made, then alignment references are available, but the distance between vias must be increased for sufficient insulation

Engineering Contradiction:
Improvealignment accuracyVSAvoidvia integration density
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by forming the via openings and applying the insulation layer before the electronic components are fabricated. This sequence allows components to be formed over the via structures using the via openings as alignment references, eliminating the need for increased spacing while maintaining precise alignment. The insulation layer is deposited conformally on the via walls before component formation, ensuring sufficient insulation without increasing via distance.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If thermal oxidation is used to form insulation, then high-quality conformal insulation is achieved, but the process temperature reaches 1000°C which causes metal diffusion into substrate

Engineering Contradiction:
Improveinsulation conformalityVSAvoidmetal diffusion
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent performs the thermal oxidation process to form high-quality conformal insulation layers before fabricating the electronic components. By completing the insulation formation early in the process sequence, the high-temperature thermal oxidation (1000°C+) is executed when no metal layers are present that could diffuse into the substrate. Subsequent component fabrication occurs at lower temperatures that do not cause diffusion, thus achieving both high insulation quality and preventing metal contamination.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides high-quality insulation suitable for high-voltage applications, increases via integration density, and ensures accurate positioning by forming vias before electronic components, resulting in improved electric performance and increased via density.

Implementation Method 1

b) thermally oxidizing walls of the openings

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS8298942B2Method for forming electric vias
Publication Date: 2012.10.30 STMICROELECTRONICS (CROLLES 2) SAS
  • US8298942B2 patent drawing
  • US8298942B2 patent drawing
  • US8298942B2 patent drawing

AI summary

A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.