Thermal Paths in Layer-Transferred Semiconductor Structures
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Solution Overview
Problem
Semiconductor-on-insulator (SOI) technology faces significant challenges in heat dissipation due to the low thermal conductivity of the insulator layer, leading to excessive heat buildup and potential device failures in integrated circuits, especially in miniaturized devices where heat generation density is high.
Innovation Solution
The introduction of thermal paths using high thermally conductive materials, such as AlN, SiC, and un-doped poly-silicon, which act as heat sinks to efficiently dissipate heat from the active circuitry to the handle wafer substrate layer, enhancing lateral heat conduction and reducing thermal resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulator layer is introduced to electronically isolate the active layer from bulk substrate, then electrical isolation performance is improved, but thermal conductivity deteriorates
Solution Approach 1:
The patent divides the thermal management function into separate components: the insulator layer maintains electrical isolation while dedicated thermal paths (made of highly thermally conductive materials) provide thermal conduction. This segmentation allows independent optimization of electrical and thermal properties without compromise.
Solution Approach 2:
The patent introduces intermediary thermal path structures between the active layer and substrate. These intermediate elements (thermal paths with high thermal conductivity materials like diamond, cubic silicon carbide, or boron nitride) act as mediators that conduct heat away from the active layer while allowing the insulator layer to maintain its electrical isolation function.
2Productivity
If device miniaturization is pursued to increase integration density, then circuit functionality is improved, but heat generation density increases
Solution Approach 1:
The patent addresses heat dissipation by introducing vertical thermal paths through the layered structure. Instead of relying solely on lateral heat spreading in miniaturized devices, the invention creates three-dimensional thermal management by conducting heat vertically from the active layer through the insulator layer via dedicated thermal paths to the substrate, adding a vertical dimension to thermal management.
Solution Approach 2:
The patent employs composite material structures combining materials with contrasting properties: the insulator layer (low thermal conductivity, high electrical isolation) is combined with thermal path materials (high thermal conductivity such as diamond, cubic silicon carbide, or boron nitride) to create a composite structure that simultaneously provides electrical isolation and efficient heat dissipation in miniaturized devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves heat dissipation in SOI and layer transferred structures, mitigating the risk of device failure by providing an efficient thermal path for heat removal, even in densely packed integrated circuits.
Implementation Method 1
The introduction of thermal paths using high thermally conductive materials, such as AlN, SiC, and un-doped poly-silicon, which act as heat sinks to efficiently dissipate heat from the active circuitry to the handle wafer substrate layer
Data Source
AI summary
A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.