Multi-layered Thermal Sensor Using Xenon Difluoride Etching
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Solution Overview
Problem
Current technologies face challenges in manufacturing compact and efficient thermal sensors with high spatial resolution and cost-effectiveness, particularly in scaling down Thermally Isolated Metal Oxide Semiconductor (TMOS) transistors while maintaining thermal isolation and aspect ratio, and in controlling isotropic etching processes for large wafers.
Innovation Solution
The method involves forming holes in a semiconductor substrate using ion etching, filling them with oxide to create supporting elements, and applying a silicon-selective, gas-based isotropic etching process using xenon fluoride to suspend oxide layers, coupled with wafer level packaging and microlenses to direct infrared radiation onto thermal semiconductor sensing elements, thereby enhancing the form factor and resolution of thermal sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion etching is used to form holes in semiconductor substrate, then manufacturing process is established, but resolution and aspect ratio are limited
Solution Approach 1:
The patent transitions from ion etching to isotropic chemical etching using xenon difluoride gas, changing the etching mechanism parameters to achieve superior resolution and aspect ratio. The chemical etching process allows for precise control of hole dimensions and achieves higher aspect ratios compared to conventional ion etching methods.
Solution Approach 2:
The patent replaces the mechanical ion etching process with a chemical etching process using xenon difluoride gas. This substitution enables finer resolution and higher aspect ratio holes through chemical reactions rather than physical sputtering, overcoming the limitations of mechanical etching methods.
2Reliability
If thermal isolation is maintained in scaled down TMOS transistors, then thermal sensing performance is improved, but device size reduction is limited
Solution Approach 1:
The patent implements a multi-layer suspended structure where oxide layers are suspended above semiconductor substrates, creating a nested configuration that maintains thermal isolation while minimizing footprint. The supporting elements connect the suspended oxide layer to the substrate, enabling compact integration without compromising thermal performance.
Solution Approach 2:
The patent moves thermal isolation from a planar configuration to a three-dimensional suspended structure. By suspending the oxide layer above the substrate and connecting it through supporting elements, the design achieves thermal isolation in the vertical dimension while reducing the horizontal footprint, enabling compact sensor design.
3Measurement precision
If microlenses are added to direct infrared radiation, then spatial resolution is improved, but device complexity increases
Solution Approach 1:
The patent integrates microlenses directly onto the sensor surface in an array configuration, with each lens corresponding to a sensing element. This segmentation allows independent optimization of each pixel's light collection while maintaining overall system compactness, improving spatial resolution without proportionally increasing complexity.
Solution Approach 2:
The patent combines the microlens array with the thermal sensor array in a single integrated structure. The microlenses are formed as part of the same fabrication process and are directly coupled to the sensing elements, merging optical functionality with sensing functionality to reduce overall device complexity despite the added resolution capability.
4Manufacturing precision
If isotropic etching process is applied for high resolution, then manufacturing precision is improved, but control difficulty for large wafers increases
Solution Approach 1:
The patent introduces a sacrificial oxide layer as an intermediary that controls the etching process. The isotropic etchant selectively removes the sacrificial oxide layer while leaving the structural oxide layers intact, providing self-limiting etching depth control. This intermediary layer acts as a stop layer that prevents over-etching and enables precise control even for large wafer sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of compact thermal sensors with improved spatial resolution and cost-effectiveness by maintaining thermal isolation and aspect ratio, while the isotropic etching process provides finer resolution and higher aspect ratio holes, and the microlenses increase the form factor, addressing the limitations of existing technologies.
Implementation Method 1
applying an isotropic etching process to remove the first semiconductor substrate and expose the supporting elements to provide a suspended first oxide layer
Implementation Method 2
the isotropic etching process may be silicon-selective, gas-based, and involves using the second oxide layer as an etch stop
Implementation Method 3
Gas based means that the etching can be done by a gas
Implementation Method 4
one or more lenses that precede the one or more thermal semiconductor sensing elements, wherein the one or more lenses may be configured (constructed and arranged) to direct infrared radiation onto the one or more thermal semiconductor sensing elements
Implementation Method 5
maintaining thermal isolation and aspect ratio
Data Source
AI summary
A method for manufacturing a thermal sensor, the method may include forming, using ion etching, one or more first holes that pass through (a) an initial layer, (a) a first oxide layer, (c) a first semiconductor substrate; filling the one or more first holes with oxide to form supporting elements; fabricating one or more thermal semiconductor sensing elements; forming one or more second holes in the one or more upper layers and the first oxide layer; applying an isotropic etching process to remove the first semiconductor substrate and expose the supporting elements to provide a suspended first oxide layer.


