Thermal Via Structure for 3D IC Heat Dissipation
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Solution Overview
Problem
Conventional 3D-ICs face heat trapping issues between stacked chips, leading to temperature rise and potential device failure, with existing cooling methods being expensive.
Innovation Solution
A 3D-IC structure and method that incorporates a thermal via structure using barrier layer metallurgy (BLM) for solder bumps, creating a heat dissipation path between chips, reducing fabrication costs by eliminating process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 3D-IC stacking is used, then high density integration is achieved, but heat trapping occurs between stacked chips causing temperature rise and device failure
Solution Approach 1:
The patent divides the die stack structure into segments by introducing void regions between chips. These voids act as thermal management zones that segment the heat flow path, allowing heat to dissipate between stacked chips rather than accumulating in a continuous solid structure.
Solution Approach 2:
The patent introduces void regions (porous spaces) between stacked chips that serve as thermal management structures. These voids facilitate heat dissipation by providing air gaps that enhance thermal convection and radiation, preventing heat trapping while maintaining the high density integration of the 3D-IC structure.
2Temperature
If microfluidic cooling or silicon spacer cooling is implemented, then heat dissipation is improved, but fabrication cost increases significantly
Solution Approach 1:
The patent employs the existing BLM (Barrier Layer Metallurgy) process steps to simultaneously create both the solder bump structures and the thermal via structures. The BLM layers are patterned to form thermal vias that extend into void regions, utilizing the same metallization processes already required for interconnect formation, thereby achieving heat dissipation without adding separate cooling fabrication steps.
Solution Approach 2:
The BLM structures serve dual functions: electrical interconnection through solder bumps and thermal management through thermal vias. By making the metallization layers multi-functional, the patent eliminates the need for separate cooling structures, reducing fabrication complexity and cost while achieving effective heat dissipation.
3Ease of manufacture
If BLM process steps are eliminated, then fabrication cost is reduced, but thermal via structure formation becomes more difficult
Solution Approach 1:
The patent merges the formation of electrical interconnect structures and thermal management structures into a single integrated process. The BLM layers are patterned and formed simultaneously for both solder bump creation and thermal via definition, combining what would traditionally be separate fabrication sequences into one unified process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively transfers and dissipates heat trapped between chips, improving chip performance and longevity while reducing fabrication costs.
Implementation Method 1
A upper portion of the thermal via is formed in the first dielectric layer and contacts the bottom surface of the first chip. A lower portion of the thermal via is formed in the second dielectric layer and contacts the bottom surface of the second chip.
Data Source
AI summary
A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.