Thermometer Code Generator for Accurate FLL VCO Locking
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Solution Overview
Problem
Conventional frequency-locked loops (FLLs) face challenges with increased complexity and error in thermometer code generation, leading to difficulties in locking the voltage-controlled oscillator (VCO) clock to a target frequency, and the duty ratio of the VCO clock is not always 50% due to separate control voltages for fine and coarse tuning.
Innovation Solution
A thermometer code generator with n bit storing stages that synchronizes up and down signals with a clock to adjust the stored code, using a maintenance signal to maintain the code when both signals are inactive, and a digital-analog converter to generate control voltages for the VCO, along with a frequency-locked loop structure that includes a phase frequency detector, charge pump, and a duty ratio corrector to ensure accurate frequency locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional decoder is used to convert binary code to thermometer code, then the frequency-locked loop can lock the VCO clock to target frequency, but the decoder complexity increases and error rate increases when bit number of counter increases
Solution Approach 1:
The patent extracts the thermometer code generation function from the conventional binary-to-thermometer decoder and implements it directly in the counter circuit using additional logic gates (AND gates and OR gates) within the counter structure. This eliminates the need for a separate complex decoder block while maintaining accurate thermometer code generation, thereby reducing overall system complexity and improving reliability.
Solution Approach 2:
The patent merges the thermometer code generation logic with the counter circuit by integrating AND gates and OR gates directly into the counter structure. This combination allows the counter to simultaneously perform binary counting and thermometer code generation in a unified circuit, reducing the number of separate components and simplifying the overall system architecture.
2Adaptability or versatility
If separate control voltages for fine tuning and coarse tuning are applied to VCO, then frequency adjustment range is improved, but duty ratio of VCO clock becomes non-50%
Solution Approach 1:
The patent introduces a feedback mechanism using a duty ratio corrector that monitors the VCO clock duty ratio and generates correction signals. When the duty ratio deviates from 50%, the corrector adjusts the control voltages applied to the VCO to restore the duty ratio, thereby maintaining stability while preserving the wide frequency tuning range enabled by separate fine and coarse control voltages.
3Reliability
If conventional FLL structure with up/down counter and decoder is used, then frequency locking function is achieved, but time delay increases and complexity increases
Solution Approach 1:
The patent merges the counter and thermometer code generation functions into a single integrated circuit block. By combining the binary counting logic with the thermometer code generation logic (using AND gates and OR gates within the counter structure), the patent eliminates the need for a separate decoder stage, thereby reducing the number of logic stages and minimizing time delay while maintaining frequency locking reliability.
Data Source
AI summary
A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.