Thermopile Pixel Fabrication with Buried Insulation and Dual-Sided Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing manufacturing techniques for infrared imagers with thermopile structures struggle to produce pixels smaller than 120 µm due to imprecision in cavity shape and alignment, and inadequate insulation between thermopile structures and CMOS circuitry, leading to increased pixel size and fabrication costs.
Innovation Solution
A method for fabricating thermopile pixels on a semiconductor substrate using buried insulation regions, involving trench formation, passivation, conformal layer deposition, and precise DRIE etching to create a cavity under the membrane with high accuracy, ensuring proper insulation and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If anisotropic etching from the back of the membrane is used, then the cavity can be formed, but the manufacturing precision and alignment accuracy are insufficient
Solution Approach 1:
The cavity formation process is segmented into multiple steps: first forming a shallow cavity from the back surface, then forming a deeper cavity from the front surface to reach the membrane. This segmentation allows each etching step to be controlled independently, achieving the required +/- 0.5 µm precision while maintaining manufacturing feasibility
Solution Approach 2:
The invention transitions from single-sided etching to dual-sided etching by introducing front surface etching as an additional dimension. This allows precise control of cavity depth and shape by coordinating etching from both surfaces, achieving the required alignment precision without excessive fabrication complexity
2Reliability
If a distance of 8-10 µm is maintained between thermopile structures and CMOS circuitry for insulation, then good insulation is achieved, but the pixel size increases significantly
Solution Approach 1:
A dielectric membrane serves as an intermediary structure between the thermopile structures and the CMOS circuitry. The membrane provides the necessary electrical insulation while allowing the thermopile to be positioned much closer to the circuitry (within 4 µm), thus maintaining reliability without increasing pixel size
Solution Approach 2:
The dielectric membrane acts as a thin film structure that provides electrical isolation between different components. This thin film approach allows for compact integration with minimal spacing requirements while maintaining the necessary insulation properties
3Area of moving object
If smaller pixel dimensions are produced, then the imager chip size and cost are reduced, but the manufacturing precision requirements become more stringent
Solution Approach 1:
The cavity formation is segmented into controlled steps from both front and back surfaces, with each step contributing to the final precise dimensions. This segmentation enables achievement of +/- 0.5 µm precision required for small pixels while using standard manufacturing processes
Solution Approach 2:
The invention replaces less precise mechanical alignment methods with a self-aligned etching approach where the cavity position is determined by the membrane location and etch mask patterns, achieving the required precision through process control rather than mechanical positioning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves +/- 0.5 µm precision in cavity formation and alignment, significantly improving the precision and reducing pixel size, allowing for closer integration of thermopile structures with CMOS circuitry within 4 µm or less, thereby reducing fabrication costs and enabling smaller pixel dimensions.
Implementation Method 1
forming a cavity in the substrate abutting the membrane and at least a portion of the trench via an unmasked region
Implementation Method 2
applying a passivation layer over the substrate first surface and the trench
Implementation Method 3
filling the trench by depositing a conformal layer of a material over the substrate first surface
Implementation Method 4
planarizing the passivation layer from the substrate first surface
Data Source
Figure 1A~1C
Figure 1D~1F
Figure 1G~1H
AI summary
A method for manufacturing an imaging device in a semiconductor substrate is disclosed. The substrate includes a first surface, a second surface substantially opposite the first surface, and a thickness defined by a distance between the first surface and the second surface. A trench is fabricated in the semiconductor substrate first surface. A passivation layer is applied over the substrate first surface and the trench, optionally filling the trench by depositing a conformal layer over the substrate first surface. The conformal layer and the passivation layer are planarized from the substrate first surface, and a membrane is fabricated on the substrate first surface. From the substrate second surface, a cavity is formed in the substrate abutting the membrane and at least a portion of the trench via the unmasked region.