Thick Conductive Stack Plating for Compact Passive On Glass
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Solution Overview
Problem
Current conductive material plating processes for thick trace layers in passive on glass technology face challenges in maintaining compact device sizes while enhancing performance, as they often require larger line widths and spacing dimensions or additional fabrication steps.
Innovation Solution
A thick conductive stack plating process with fine critical dimension feature size is developed, involving sequential stacking and patterning with a single photoresist layer, eliminating the need for interlayer dielectric formation and reducing the number of process steps, thereby maintaining compact size and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive material plating processes are used to increase conductive material thickness, then device performance is improved, but critical dimension feature size increases
Solution Approach 1:
The patent transitions from planar (2D) conductive traces to vertically stacked (3D) conductive layers. By stacking multiple thin conductive layers (e.g., four 5um layers instead of one 20um layer), the effective conductive thickness is increased without increasing the lateral critical dimensions. This dimensional transition resolves the contradiction between improving device performance through thicker conductors and maintaining fine feature sizes.
Solution Approach 2:
The patent divides a single thick conductive layer into multiple thinner stacked layers. Each layer is patterned separately with fine critical dimensions, then stacked vertically to achieve the desired effective thickness. This segmentation allows each layer to maintain small feature sizes while the stack collectively provides the performance benefits of thicker conductors.
2Reliability
If conventional plating processes are used to enhance device performance, then conductive material thickness increases, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple conductive layer depositions and patterning operations into an integrated stacked layer process. Rather than treating each conductive layer as a separate device feature requiring independent processing, the methodology merges them into a unified stack structure that is processed collectively, reducing overall manufacturing complexity despite the increased number of layers.
Solution Approach 2:
By moving to vertical stacking, the patent consolidates multiple thin layers into a compact vertical structure rather than requiring large lateral spacing. This dimensional change reduces the overall device footprint and simplifies the manufacturing process by eliminating the need for complex lateral routing and spacing management.
3Reliability
If thicker conductive layers are used to improve performance, then device size increases, but compact device design is compromised
Solution Approach 1:
The patent resolves the size conflict by transitioning from lateral expansion to vertical stacking. Instead of increasing the lateral dimensions to accommodate thicker conductors, the solution stacks multiple thin layers vertically, maintaining the original lateral footprint while achieving the desired effective conductive thickness for improved performance.
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers are stacked one on top of another, similar to nested dolls. Each layer is contained within the vertical structure, allowing the device to achieve thick conductor equivalence without increasing the lateral device area, thus maintaining compact design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process increases conductive material thickness without enlarging critical design features, resulting in smaller, more efficient devices with reduced manufacturing costs and improved performance for high-Q components like spiral inductors.
Implementation Method 1
depositing a first photoresist layer on a first interlayer dielectric layer and a substrate
Implementation Method 2
depositing a first conductive layer between gaps in the first photoresist layer
Implementation Method 3
depositing a second conductive layer directly on the first conductive layer
Data Source
AI summary
An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.