Thick Copper Interconnection Structure Annealing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional copper interconnection structures in semiconductor manufacturing exhibit poor electrical performance due to limited copper grain growth during thermal annealing, as the integration level increases and feature sizes shrink, restricting the reduction in resistance.
Innovation Solution
A method involving a conductive film with a first thickness greater than its initial grain size, undergoing an annealing process to transform the lattice structure and increase grain size, followed by etching to form conductive layers and trenches for interconnection wires and vias, allowing for enhanced electrical performance without significant thinning of the film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electroplating and annealing processes are used to form copper interconnection structures, then the manufacturing process is simple and well-established, but the copper grain size remains limited and electrical performance is poor
Solution Approach 1:
The patent applies preliminary action by forming a thick copper film (greater than 1 micrometer) before annealing, which provides sufficient material thickness to accommodate significant grain growth during thermal processing. This preliminary thick-film formation enables subsequent grain growth to occur without compromising the final interconnection structure dimensions, thereby improving electrical performance while managing process complexity
Solution Approach 2:
The patent changes key parameters including copper film thickness (increased to >1 micrometer), annealing temperature (raised to 400-450°C), and annealing time (extended to 30-60 minutes). These parameter changes enable substantial copper grain growth (from sub-micrometer to several micrometers), which directly improves electrical conductivity by reducing grain boundary scattering effects
2Productivity
If the conductive film thickness is reduced to accommodate smaller feature sizes in ULSI, then the device integration level increases, but the copper grain size cannot grow sufficiently and resistance increases
Solution Approach 1:
The patent transitions from thin-film interconnections to thick-film interconnections by increasing the copper film thickness dimension to greater than 1 micrometer. This dimensional change provides sufficient thickness to accommodate large grain growth during annealing while still fitting within the vertical budget of advanced technology nodes, thereby maintaining integration levels while improving conductivity
Solution Approach 2:
The patent changes the copper film thickness parameter from conventional thin-film dimensions (sub-100nm) to thick-film dimensions (>1 micrometer). This parameter change enables the copper grains to grow to several micrometers during annealing without being constrained by film thickness, thus maintaining low resistance even as feature sizes shrink for higher integration
3Reliability
If extensive annealing is performed to grow copper grains and reduce resistance, then electrical performance improves, but the film thickness decreases due to thermal thinning and morphology degrades
Solution Approach 1:
The patent applies beforehand cushioning by forming a thick copper film (greater than 1 micrometer) before annealing. This excess thickness acts as a cushion that absorbs the thickness loss and morphology degradation that occur during extensive high-temperature annealing, ensuring that the final interconnection structure maintains adequate dimensions and acceptable morphology after grain growth is complete
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in conductive interconnection structures with reduced resistance and improved electrical performance, enabling better conductivity and integration capabilities while maintaining desired morphology.
Implementation Method 1
performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size
Implementation Method 2
etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench
Data Source
AI summary
An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.