Thick Insulating Film for Semiconductor Surface Flatness
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face issues with surface flatness and electrostatic discharge immunity due to dishing of silicon oxide films in trenches, which affects the accuracy of resist patterns and reliability of resistance elements, and require increased chip area for dummy active regions to improve surface flatness.
Innovation Solution
The approach involves forming high voltage MISFETs and resistance elements on a semiconductor substrate with a thick insulating film at the same level, allowing resistance elements to be formed over active regions without significant dummy active regions, thereby reducing chip size and improving surface flatness and ESD immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy active regions are added to improve surface flatness, then surface flatness is improved, but chip area increases
Solution Approach 1:
The patent applies preliminary action by forming a thick insulating film (60-100 nm) in advance before creating element isolating trenches. This pre-formed thick film serves as a buffer that prevents dishing from affecting the final surface flatness, eliminating the need for dummy active regions and reducing chip area.
Solution Approach 2:
The patent changes the parameter of insulating film thickness from conventional thin films to thick films (60-100 nm) in element isolating regions. This parameter change provides sufficient material buffer to prevent dishing, improving surface flatness without requiring additional dummy structures that would increase chip area.
2Adaptability or versatility
If element isolating trenches are made larger to accommodate resistance elements, then resistance elements can be formed, but dishing of silicon oxide film occurs
Solution Approach 1:
The thick insulating film is formed preliminarily before trench formation, providing a sufficient material buffer that prevents dishing even in large trenches. This allows resistance elements to be formed in element isolating regions without causing surface flatness deterioration.
Solution Approach 2:
By changing the insulating film thickness parameter to 60-100 nm (thick film), the patent provides enough material buffer to prevent dishing in large element isolating trenches, enabling resistance element formation while maintaining surface flatness.
3Ease of manufacture
If thin silicon oxide film is used in element isolating trenches, then manufacturing is simpler, but surface flatness deteriorates due to dishing
Solution Approach 1:
The patent changes the film thickness parameter from thin to thick (60-100 nm), which naturally prevents dishing without complicating the manufacturing process. The thick film provides sufficient buffer material that remains flat after CMP, maintaining both manufacturing simplicity and surface flatness.
Data Source
AI summary
A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.