Thick Logic Die Package Layout for PoP Thermal Dissipation
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Solution Overview
Problem
Current semiconductor package technologies face challenges in thermal dissipation efficiency, which is crucial for improving the reliability and durability of Package-on-Package (PoP) structures used in high-end mobile devices.
Innovation Solution
The proposed solution involves a semiconductor package design with a thick logic die mounted on a bottom substrate in a flip-chip fashion, accompanied by a memory die, where a connection structure and sealing resin are used to enhance thermal performance. This design includes a stiffener frame and a re-distribution layer to manage signal transmission and thermal dissipation effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional PoP structures are used, then component density is improved, but thermal dissipation efficiency deteriorates
Solution Approach 1:
The patent transitions from vertical stacking (PoP) to a side-by-side planar arrangement of logic and memory dies on the same substrate. This dimensional change from vertical to lateral configuration reduces thermal interference between components while maintaining high component density, thereby improving thermal dissipation efficiency without sacrificing integration level.
2Temperature
If thick logic die is used, then thermal dissipation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies a logic die thickness parameter of not less than 125 micrometers, which is substantially thicker than conventional dies. This parameter change increases the die's thermal mass and heat dissipation capability. The thick die design is implemented through standard semiconductor manufacturing processes, balancing improved thermal performance with manufacturing feasibility.
3Temperature
If side-by-side arrangement is used, then thermal dissipation is improved, but package height increases
Solution Approach 1:
The patent arranges logic and memory dies side-by-side in the planar direction rather than stacking them vertically. This reconfiguration shifts the spatial arrangement from the vertical dimension to the horizontal dimension, improving thermal dissipation through reduced thermal coupling while maintaining a compact package height suitable for mobile devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced thermal dissipation capabilities improve the performance and reliability of semiconductor packages, addressing the thermal throttle issue and reducing package height compared to conventional PoP structures.
Implementation Method 1
The enhanced thermal dissipation capabilities improve the performance and reliability of semiconductor packages
Implementation Method 2
the logic die is electrically connected to the bottom substrate through a plurality of conductive elements formed on the plurality of I/O pads, respectively
Data Source
AI summary
A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.