Thick Logic Die PoP Package for Thermal and Interconnect Efficiency
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Solution Overview
Problem
Current semiconductor package technologies face challenges in enhancing thermal dissipation and interconnect efficiency, particularly in Package-on-Package (PoP) structures used in high-end mobile devices, which require improved performance and reliability.
Innovation Solution
A thermally enhanced semiconductor package design featuring a thick logic die mounted on a bottom substrate with copper cored solder balls and sealing resin, creating a gap between substrates to facilitate electrical connection and thermal management, along with a flip-chip configuration and underfill resin for enhanced stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick logic die is used to improve thermal dissipation and interconnect efficiency, then thermal management and electrical connection are enhanced, but the package height and structural complexity increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple substrates (bottom substrate, top substrate, and intermediate substrate) with a thick logic die in between. This vertical stacking approach allows thermal dissipation pathways to extend in the Z-direction, improving heat removal efficiency while maintaining a compact footprint. The gap between substrates is optimized to balance thermal conduction path length with mechanical stability.
Solution Approach 2:
The thick logic die (125-350 micrometers) is nested between the bottom substrate and top substrate, with copper cored solder balls positioned around it. The sealing resin further nests around the logic die and solder balls, creating a compact integrated structure. This nested arrangement allows the thick die to be accommodated without excessive increase in overall package dimensions.
2Reliability
If copper cored solder balls are used to improve electrical connection and thermal conduction, then interconnect efficiency is enhanced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs copper cored solder balls that combine copper (for thermal conduction) with solder material (for electrical connection and mechanical bonding). This composite structure leverages the high thermal conductivity of copper while maintaining the electrical and mechanical properties of solder, achieving dual functionality in a single component that simplifies the overall interconnect design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves thermal dissipation and interconnect efficiency, enhancing the performance and reliability of semiconductor packages by optimizing the gap height, solder ball aspect ratio, and resin sealing, thereby supporting higher performance in applications like high-end mobile devices.
Implementation Method 1
a plurality of copper cored solder balls disposed between the bottom substrate and the top substrate around the logic die
Implementation Method 2
a sealing resin filling in the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap
Implementation Method 3
underfill resin is disposed in a space between the logic die and the top surface of the bottom substrate, and wherein the conductive elements are surrounded by the underfill resin
Data Source
Figure 1
Figure 2
AI summary
A semiconductor package (10) includes a bottom substrate (100) and a top substrate (300) space apart from the bottom substrate (100) such that the bottom substrate (100) and the top substrate (300) define a gap therebetween. A logic die (50) is mounted on a top surface (100a) of the bottom substrate (100). The logic die (50) has a thickness of 125-350 micrometers. A plurality of copper cored solder balls (60) is disposed between the bottom substrate (100) and the top substrate (300) around the logic die (50) to electrically connect the bottom substrate (100) with the top substrate (300). A sealing resin (SM) fills into the gap between the bottom substrate (100) and the top substrate (300) and sealing the logic die (50) and the plurality of copper cored solder balls (60) in the gap.