Thick Logic Die Package Structure for Better Thermal Dissipation
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Solution Overview
Problem
Current semiconductor packaging technologies, particularly Package-on-Package (PoP) solutions, face challenges in thermal dissipation efficiency and interconnect performance, which are crucial for high-performance devices like mobile phones.
Innovation Solution
A thermally enhanced semiconductor package design featuring a thick logic die mounted on a bottom substrate with copper cored solder balls and a sealing resin to create a gap between substrates, enhancing thermal performance and interconnects by using a flip-chip configuration and specific materials like silicon nitride and gold-nickel bump structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional thin logic die packaging is used, then device assembly is simpler, but thermal dissipation efficiency deteriorates
Solution Approach 1:
The patent changes the thickness parameter of the logic die from conventional thin (e.g., 80 μm) to thick (125-350 μm), which fundamentally alters the thermal conduction path and improves thermal dissipation efficiency while maintaining electrical performance
Solution Approach 2:
The patent employs composite material structures including copper cored solder balls (copper core with solder coating), multi-layer bump structures (gold and nickel layers), and sealing resins to enhance thermal conduction while providing mechanical support and protection
2Temperature
If thicker logic die is used, then thermal dissipation improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes a specific thickness range (125-350 μm) for the logic die that balances thermal performance with manufacturability, avoiding excessive thickness that would be difficult to manufacture while ensuring sufficient thermal conduction
Solution Approach 2:
The copper cored solder balls and bump structures serve as intermediary thermal conduction elements between the thick logic die and the substrate, facilitating heat transfer while accommodating manufacturing tolerances
3Temperature
If copper cored solder balls are used for interconnects, then thermal conduction improves, but manufacturing complexity increases
Solution Approach 1:
The patent uses copper cored solder balls with a copper core for thermal conduction and solder coating for bonding, creating a composite interconnect structure that achieves both thermal performance and manufacturability through a single component
Solution Approach 2:
The patent combines thermal conduction function and electrical connection function into a single copper cored solder ball component, eliminating the need for separate thermal management and electrical interconnect structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves thermal dissipation and interconnect performance, enabling higher efficiency and reliability in semiconductor packages, particularly in high-end mobile devices.
Implementation Method 1
A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die
Implementation Method 2
A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap
Data Source
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AI summary
A semiconductor package (10) includes a bottom substrate (100) and a top substrate (300) space apart from the bottom substrate (100) such that the bottom substrate (100) and the top substrate (300) define a gap therebetween. A logic die (50) is mounted on a top surface (100a) of the bottom substrate (100) in a flip-chip fashion. The logic die (50) has a thickness of 125-350 micrometers. The logic die (50) comprises an active front side (50a), a passive rear side (50b), and an input/output pad (501) provided on the active front side (50a). A plurality of copper cored solder balls (60) is disposed between the bottom substrate (100) and the top substrate (300) around the logic die (50) to electrically connect the bottom substrate (100) with the top substrate (300). A sealing resin (SM) fills in the gap between the bottom substrate (100) and the top substrate (300) and seals the logic die (50) and the plurality of copper cored solder balls (60) in the gap.